M40Z300MQ1(2000) データシートの表示（PDF） - STMicroelectronics

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M40Z300MQ1
(Rev.:2000)

NVRAM CONTROLLER for up to EIGHT LPSRAM

STMicroelectronics 

Figure 4. Hardware Hookup

3.0V, 3.3V or 5V

M40Z300, M40Z300W

VCC VOUT

0.1µF

M40Z300

M40Z300W

A

E1CON

E2CON

B

E3CON

E

E4CON

VCC

0.1µF

CMOS

SRAM

E

VCC

0.1µF

CMOS

SRAM

E

Threshold THS

RST

To Microprocessor

VSS

BL

To Battery Monitor Circuit

VCC

0.1µF

CMOS

SRAM

E

VCC

0.1µF

CMOS

SRAM

E

AI02395

POWER-ON RESET OUTPUT

All microprocessors have a reset input which forc-

es them to a known state when starting. The

M40Z300/W has a reset output (RST) pin which is

guaranteed to be low within tWPT of VPFD (See Ta-

ble 7). This signal is an open drain configuration.

An appropriate pull-up resistor should be chosen

to control the rise time. This signal will be valid for

all voltage conditions, even when VCC equals VSS.

Once VCC exceeds the power failure detect volt-

age VPFD, an internal timer keeps RST low for

tREC to allow the power supply to stabilize.

TWO TO FOUR DECODE

The M40Z300/W includes a 2 input (A, B) decoder

which allows the control of up to 4 independent

SRAMs. The Truth Table for these inputs is shown

in Table 3.

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