M38020E1-XXXFP データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M38020E1-XXXFP

8-BIT SINGLE-CHIP MICROCOMPUTER

MITSUBISHI ELECTRIC  

List of figures

Fig. 2.3.21 Control procedure at a transmitting side

[Communication using a clock synchronous serial I/O] .................................. 2-36

Fig. 2.3.22 Control procedure at a receiving side[Communication using a clock synchronous serial I/O] .. 2-37

Fig. 2.3.23 Connection diagram [Output of serial data] ......................................................... 2-38

Fig. 2.3.24 Timing chart [Output of serial data] ...................................................................... 2-38

Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data] .......................... 2-39

Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data]........................ 2-39

Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data] .................................... 2-40

Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data] .......................... 2-41

Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data]........................ 2-41

Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data] .................................... 2-42

Fig. 2.3.31 Connection diagram

[Cyclic transmission or reception of block data between microcomputers] .. 2-43

Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers] .......... 2-44

Fig. 2.3.33 Setting of related registers

[Cyclic transmission or reception of block data between microcomputers] .. 2-44

Fig. 2.3.34 Control in the master unit ....................................................................................... 2-45

Fig. 2.3.35 Control in the slave unit .......................................................................................... 2-46

Fig. 2.3.36 Connection diagram [Communication using UART] ............................................ 2-47

Fig. 2.3.37 Timing chart [Communication using UART] ......................................................... 2-47

Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART] ........................ 2-49

Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART] ............................ 2-50

Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART] .......... 2-51

Fig. 2.3.41 Control procedure at a receiving side [Communication using UART] ............. 2-52

Fig. 2.4.1 Memory map of PWM related registers .................................................................. 2-53

Fig. 2.4.2 Structure of PWM control register ............................................................................ 2-54

Fig. 2.4.3 Structure of PWM prescaler ...................................................................................... 2-54

Fig. 2.4.4 Structure of PWM register ......................................................................................... 2-55

Fig. 2.4.5 Connection diagram .................................................................................................... 2-56

Fig. 2.4.6 PWM output timing ..................................................................................................... 2-56

Fig. 2.4.7 Setting of related registers ........................................................................................ 2-57

Fig. 2.4.8 PWM output ................................................................................................................. 2-57

Fig. 2.4.9 Control procedure ....................................................................................................... 2-58

Fig. 2.5.1 Memory map of A-D conversion related registers ................................................ 2-59

Fig. 2.5.2 Structure of AD/DA control register ........................................................................ 2-60

Fig. 2.5.3 Structure of A-D conversion register ...................................................................... 2-60

Fig. 2.5.4 Structure of Interrupt request register 2 ................................................................ 2-61

Fig. 2.5.5 Structure of Interrupt control register 2 ................................................................. 2-61

Fig. 2.5.6 Connection diagram [Conversion of Analog input voltage] ................................. 2-62

Fig. 2.5.7 Setting of related registers [Conversion of Analog input voltage] ..................... 2-62

Fig. 2.5.8 Control procedure [Conversion of Analog input voltage]..................................... 2-63

Fig. 2.6.1 Memory map of processor mode related register ................................................ 2-64

Fig. 2.6.2 Structure of CPU mode register .............................................................................. 2-64

Fig. 2.6.3 Expansion example of ROM and RAM .................................................................. 2-65

Fig. 2.6.4 Read-cycle (OE access, SRAM) ............................................................................. 2-66

Fig. 2.6.5 Read-cycle (OE access, EPROM) .......................................................................... 2-66

Fig. 2.6.6 Write-cycle (W control, SRAM)................................................................................. 2-67

Fig. 2.6.7 Application example of the ONW function ............................................................. 2-68

3802 GROUP USER’S MANUAL

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