BS62LV2005TI データシートの表示（PDF） - Brilliance Semiconductor
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BS62LV2005TI Datasheet PDF : 10 Pages
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BSI
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC TEST LOADS AND WAVEFORMS
5.0V
OUTPUT
1928 Ω
5.0V
OUTPUT
1928 Ω
INCLUDING
JIG AND
SCOPE
100PF
1020Ω
INCLUDING
JIG AND
SCOPE
5PF
1020 Ω
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
667 Ω
1.73V
ALL INPUT PULSES
Vcc
GND
10%
→
90% 90%
←
→
FIGURE 2
10%
← 5ns
BS62LV2005
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 5.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
tAVAX
tAVQV
t
E1LQV
tE2HOV
tGLQV
t
E1LQX
tE2HOX
tGLQX
tE1HQZ
tE2HQZ
tGHQZ
tAXOX
PARAMETER
NAME
tRC
tAA
t
ACS1
tACS2
tOE
t
CLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
tOH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
Output Disable to Output Address Change
BS62LV2005-55
MIN. TYP. MAX.
55
--
--
--
--
55
--
--
55
--
--
55
--
--
30
10
--
--
10
--
--
10
--
--
0
--
30
0
--
30
0
--
25
10
--
--
BS62LV2005-70
MIN. TYP. MAX.
70
--
--
--
--
70
--
--
70
--
--
70
--
--
35
10
--
--
10
--
--
10
--
--
0
--
35
0
--
35
0
--
30
10
--
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS62LV2005
4
Revision 2.4
April 2002
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