M37640E8FP データシートの表示（PDF） - Mitsumi
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M37640E8FP Datasheet PDF : 96 Pages
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Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2.4 TIMING REQUIREMENTS AND SWITCHING CHARACTERISCTICS
Table 2.4 Timing Requirements and Switching Characterisctics
(Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Symbol
Parameter
Inputs
tw(RESET)
tc(Xin)
twh(Xin)
twl(Xin)
tc(XCin)
twh(XCin)
twl(XCin)
Interrupts
tc(INT)
twh(INT)
twl(INT)
tc(CNTRI)
twh(CNTRI)
twl(CNTRI)
Timers
td(Φ-TOUT)
td(Φ-CNTR0)
tc(CNTRE0)
twh(CNTRE0)
twl(CNTRE0)
td(Φ-CNTR1)
tc(CNTRE1)
twh(CNTRE1)
twl(CNTRE1)
SIO
tc(SCLKE)
twh(SCLKE)
twl(SCLKE)
tsu(SRXD-SCLKE)
th(SCLKE-SRXD)
td(SCLKE-S__T_X_D_ )
tv(SCLKE-SRDY)
tc(SCLKI)
twh(SCLKI)
twl(SCLKI)
tsu(SRXD-SCLKI)
th(SCLKI-SRXD)
td(SCLKI-STXD)
RESET input “Low” pulse width
Clock input cycle time
Clock input “High” pulse width
Clock input “Low” pulse width
Clock input cycle time
Clock input “High” pulse width
Clock input “Low” pulse width
INT0, INT1 input cycle time
INT0, INT1 input “High” pulse width
INT0, INT1 input “Low” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “High” pulse width
CNTR0, CNTR1 input “Low” pulse width
TIMER TOUT delay time (Note)
TIMER CNTR0 delay time (pulse output mode) (Note)
TIMER CNTR0 input cycle time (event counter mode)
TIMER CNTR0 input “High” pulse width (event counter mode)
TIMER CNTR0 input “Low” pulse width (event counter mode)
TIMER CNTR1 delay time (pulse output mode) (Note)
TIMER CNTR1 input cycle time (event counter mode)
TIMER CNTR1 input “High” pulse width (event counter mode)
TIMER CNTR1 input “Low” pulse width (event counter mode)
SIO external clock input cycle time
SIO external clock input “High” pulse width
SIO external clock input “Low” pulse width
SIO receive setup time (external clock)
SIO receive hold time (external clock)
SIO t_ra__n_s_mit delay time (external clock)
SIO SRDY valid time (external clock)
SIO internal clock output cycle time
SIO internal clock output “High” pulse width
SIO internal clock output “Low” pulse width
SIO receive setup time (internal clock)
SIO receive hold time (internal clock)
SIO transmit delay time (internal clock)
Limits
Unit
Min
Typ. Max
2
_s
41.66
ns
0.4*tc(Xin)
ns
0.4*tc(Xin)
ns
200
ns
0.4*tc(XCin)
ns
0.4*tc(XCin)
ns
200
ns
90
ns
90
ns
200
ns
80
ns
80
ns
200
0.4*tc(CNTRE0)
0.4*tc(CNTRE0)
200
0.4*tc(CNTRE1)
0.4*tc(CNTRE1)
15
ns
15
ns
ns
ns
ns
15
ns
ns
ns
ns
400
190
180
15
10
166.66
0.5*tc(SCLKI)-5
0.5*tc(SCLKI)-5
20
5
ns
ns
ns
ns
ns
25
ns
26
ns
ns
ns
ns
ns
ns
5
ns
83
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