M66281FP データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M66281FP

5120 x 8-BIT x 2 LINE MEMORY

MITSUBISHI ELECTRIC  

MITSUBISHI <DIGITAL ASSP>

M66281FP

5120 x 8-BIT x 2 LINE MEMORY

VARIABLE LENGTH DELAY BIT

• 1 line (5120 bits) delay

Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read

cycle to easily make 1 line delay.

0 cycle

WCK

RCK

WRESB

RRESB

tRESS tRESH

1 cycle

2 cycle

5120 cycle 5121 cycle 5122 cycle

5118 cycle 5119 cycle (0')

(1')

(2')

tDS tDH

tDS tDH

Dn

(0)

(1)

(2)

(5117)

(5118)

(5119)

(0')

(1')

(2')

(3')

Q0n

(Q1n)

5120 cycle

tAC

tOH

(0)

(1)

(2)

(3)

WEB, REB = "L"

• n-bit delay bit

(Reset at cycles according to the delay length)

0 cycle

1 cycle 2 cycle

WCK

RCK

WRESB

RRESB

tRESS tRESH

tDS tDH

Dn

(0)

(1)

(2)

n cycle n+1 cycle n+2 cycle n+3 cycle

n-2 cycle n-1 cycle

(0')

(1')

(2')

(3')

tRESS tRESH

(n-3)

(n-2)

tDS tDH

(n-1)

(0')

(1')

(2')

(3')

Q0n

(Q1n)

m cycle

tAC

tOH

(0)

(1)

(2)

(3)

WEB, REB = "L"

m≥3

10

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