LXT9785 データシートの表示（PDF） - Intel

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LXT9785

Advanced 8-Port 10/100 Mbps PHY Transceivers

Intel 

Contents

Revision Number: 006 (INTERNAL RELEASE)

Revision Date: June 10, 2003

Page Description

200 Modified Table 83 “Control Register (Address 0)”.

201 Modified Table 84 “Status Register (Address 1)”.

204 Modified Table 87 “Auto-Negotiation Advertisement Register (Address 4)”.

205 Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register (Address 5)”.

207 Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register (Address 8)”.

207 Modified Table 92 “Port Configuration Register (Address 16, Hex 10)”.

209 Modified Table 93 “Quick Status Register (Address 17, Hex 11)”.

211 Modified Table 94 “Interrupt Enable Register (Address 18, Hex 12)”

212

Modified Table 95 “Interrupt Status Register (Address 19, Hex 13)”. Changed all references of RO/

SC to R/LH.

214 Modified Table 97 “Receive Error Count Register (Address 21, Hex 15)”.

215

Modified Table 98 “RMII Out-of-Band Signaling Register (Address 25, Hex 19)”. Added note to

Register bit 25.0.

216 Modified Table 99 “Trim Enable Register (Address 27, Hex 1B)”.

227 Modified Table 103 “Product Information”.

Page

1

49

70

109

110

111

112

112

114

129

131

133

Revision Number: 005

Revision Date: January 2002

Description

Added bullet to Product Features

Modified Table 12 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions” (Added

FIFOSEL1 and FIFOSEL0)

Added Section 2.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced

Speed Mode”

Modified Figure 38 “Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver

Interface Circuitry”

Added Figure 39 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface

Circuitry”

Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator”

Modified Table 28 “Absolute Maximum Ratings”

Modified Table 29 “Operating Conditions”

Modified Table 31 “Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)”(Output low

voltage SD pins - Max)

Modified Figure 53 “RMII - 100BASE-TX Receive Timing” and Table 49 “RMII - 100BASE-TX

Receive Timing Parameters”

Modified Figure 55 “RMII - 100BASE-FX Receive Timing” and Table 51 “RMII - 100BASE-FX

Receive Timing Parameters”

Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive

Timing Parameters”

14

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

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