LXT9785 データシートの表示（PDF） - Intel

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コンポーネント説明

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LXT9785

Advanced 8-Port 10/100 Mbps PHY Transceivers

Intel 

Contents

Revision Number: 006 (INTERNAL RELEASE)

Revision Date: June 10, 2003

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Description

Changed "pseudo-ECL (PECL)" to "Low Voltage Positive Emitter Coupled Logic (LVPECL)" in the

second paragraph, front page.

Modified Table 5 “Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP”. Added last

sentence to RXER0 through RXER7 signal description.

Modified Table 10 “Intel® LXT9785/LXT9785E Signal Detect – PQFP”.

Modified Table 11 “Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP”,

Modified Table 13 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP”. Added

note to PREASEL signal description.

Modified Section 4.1, “Introduction”. Changed "Pseudo-ECL (PECL)" to "Low Voltage PECL

(LVPECL)" in the first paragraph, second sentence.

Replace text under Section 4.2.1.3, “Fiber Interface”.

Modified Section 4.3.2, “Internal Loopback”.

Modified last sentence under Section 4.6.1.4, “Link Criteria”.

Modified text under Section 4.6.1.5, “Parallel Detection”. Added second paragraph.

Modified text under Section 4.7.4.3, “Receive Error”.

Changed "PECL" to "LVPECL in third paragraph, first sentence under Section 4.9.1, “100BASE-X

Network Operations”.

Modified Figure 28 “Intel® LXT9785/LXT9785E Protocol Sublayers”.

Modified Section 4.9.3.3, “Carrier Sense/Data Valid (RMII)”. Changed “asynchronously to

“synchronously.”

Modified text under Section 4.9.3.4, “Carrier Sense (SMII)”. Revised last sentence in first paragraph.

Modified paragraph under Section 4.9.3.6.3, “Polarity Correction”.

Replaced text under Section 4.9.3.7, “Fiber PMD Sublayer”.

Modified Section 4.10.1, “Preamble Handling”. Added text to last paragraph.

Modified first sentence under Section 4.10.4, “Jabber”.

Modified first paragraph of Section 4.11, “DTE Discovery Process”.

Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”.

Modified Section 4.12.3, “Out-of-Band Signaling”. Added sentence to end of first paragraph.

Replaced text under Section 5.2.5, “The Fiber Interface”.

Replaced Figure 36 “Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver

Interface Circuitry”.

Replaced Figure 37 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface

Circuitry”.

Modified Table 52 “Intel® LXT9785/LXT9785E Operating Conditions”.

Modified Table 53 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO =

2.5 V +/- 5%)”.

Modified Table 54 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO =

3.3 V +/- 5%)”.

Added Table 55 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins”.

Modified Table 58 “Intel® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”.

Datasheet

13

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

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