LTC4306C データシートの表示（PDF） - Linear Technology
部品番号
コンポーネント説明
一致するリスト
LTC4306C Datasheet PDF : 20 Pages
| |||
U
OPERATIO
Register 2 (02h)
BIT NAME
TYPE* DESCRIPTION
d7 GPIO1 Mode
Configure
R/W Configures Input/Output mode of
GPIO1
0 = output mode (default)
1 = input mode
d6 GPIO2 Mode
Configure
R/W Configures Input/Output Mode of
GPIO2
0 = output mode (default)
1 = input mode
d5 Connection
Requirement
R/W Sets logic requirements for
downstream buses to be connected
to upstream bus
0 = Bus Logic State bits (see register
3) of buses to be connected must be
high for connection to occur (default)
1 = Connect regardless of
downstream logic state
d4 GPIO1 Output
Mode Configure
R/W Configures GPIO1 Output Mode
0 = open-drain pull-down (default)
1 = push-pull
d3 GPIO2 Output
Mode Configure
R/W Configures GPIO2 Output Mode
0 = open-drain pull-down (default)
1 = push-pull
d2 Mass Write Enable
R/W Enable Mass Write Address using
address (1011 101)b
0 = Disable Mass Write
1 = Enable Mass Write (default)
d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1**
d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0**
* For Type, “R/W” = Read Write, “R” = Read Only
**Stuck bus program table
TIMSET1
TIMSET0
TIMEOUT MODE
0
0
Timeout Disabled (Default)
0
1
Timeout After 30ms
1
0
Timeout After 15ms
1
1
Timeout After 7.5ms
LTC4306
Register 3 (03h)
BIT NAME
TYPE* DESCRIPTION
d7 Bus 1 FET State
R/W Sets and indicates state of FET
switches connected to downstream
bus 1
0 = switch open (default)
1 = switch closed
d6 Bus 2 FET State
R/W Sets and indicates state of FET
switches connected to downstream
bus 2
0 = switch open (default)
1 = switch closed
d5 Bus 3 FET State
R/W Sets and indicates state of FET
switches connected to downstream
bus 3
0 = switch open (default)
1 = switch closed
d4 Bus 4 FET State
R/W Sets and indicates state of FET
switches connected to downstream
bus 4
0 = switch open (default)
1 = switch closed
d3 Bus 1 Logic State
R Indicates logic state of downstream
bus 1; only valid when disconnected
from upstream bus†
0 = SDA1, SCL1 or both are below 1V
1 = SDA1 and SCL1 are both above
1V
d2 Bus 2 Logic State
R Indicates logic state of downstream
bus 2; only valid when disconnected
from upstream bus†
0 = SDA2, SCL2 or both are below 1V
1 = SDA2 and SCL2 are both above
1V
d1 Bus 3 Logic State
R Indicates logic state of downstream
bus 3; only valid when disconnected
from upstream bus†
0 = SDA3, SCL3 or both are below 1V
1 = SDA3 and SCL3 are both above
1V
d0 Bus 4 Logic State
R Indicates logic state of downstream
bus 4; only valid when disconnected
from upstream bus†
0 = SDA4, SCL4 or both are below 1V
1 = SDA4 and SCL4 are both above
1V
* For Type, “R/W” = Read Write, “R” = Read Only
† These bits give the logic state of disconnected downstream buses to
the master, so that the master can choose not to connect to a low
downstream bus. A given bit is a “don’t care” if its associated
downstream bus is already connected to the upstream bus.
4306f
9
Share Link: 