LH52258A データシートの表示（PDF） - Sharp Electronics

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LH52258A

CMOS 32K × 8 Static RAM

Sharp Electronics 

CMOS 32K × 8 Static RAM

LH52258A

TIMING DIAGRAMS – WRITE CYCLE

Addresses must be stable during Write cycles. The

outputs will remain in the High-Z state if W is LOW when

E goes LOW. If G is HIGH, the outputs will remain in the

High-Z state. Although these examples illustrate timing

with G active, it is recommended that G be held HIGH for

all Write cycles. This will prevent the LH52258A’s outputs

from becoming active, preventing bus contention,thereby

reducing system noise.

Write Cycle No. 1 (W Controlled)

Chip is selected: E is LOW, G is LOW. Using only W

to control Write cycles may not offer the best performance

since both tWHZ and tDW timing specifications must be

met.

Write Cycle No. 2 (E Controlled)

G is LOW. DQ lines may transition to Low-Z if the falling

edge of W occurs after the falling edge of E.

ADDRESS

W

DQ

DATA ON

DQ LINES

tWC

VALID ADDRESS

tAW

tAH

tAS

tWP

tWHZ

tDW

tWLZ

tDH

PREVIOUS OUTPUT

HIGH-Z

INPUT

Figure 7. Write Cycle No. 1

LOW-Z

52258A-7

ADDRESS

E

W

DQ

DATA ON

DQ LINES

tWC

VALID ADDRESS

tEW

tAS

tWP

tAH

tELZ

tWHZ

tDW

tDH

HIGH-Z

LOW-Z HIGH-Z

INPUT

Figure 8. Write Cycle No. 2

52258A-8

7

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