LH51BV1000JY-70LL データシートの表示（PDF） - Sharp Electronics

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LH51BV1000JY-70LL

CMOS 1M (128K × 8) Static Ram

Sharp Electronics 

LH51BV1000J

CMOS 1M (128K × 8) Static RAM

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

CE1

CE2

10

ROW 1024

DECODER

ADDRESS

BUFFER

7

COLUMN 128

DECODER

MEMORY

CELL ARRAY

(1024 x 128 x 8)

128 x 8

COLUMN GATE

8

CE1, CE2

CONTROL

LOGIC

VCC

GND

WE

OE, WE

CONTROL

OE

LOGIC

I/O BUFFER

I/O1 I/O2 I/O3 I/O4 I/O5I/O6 I/O7I/O8

Figure 2. LH51BV1000JY Block Diagram

PIN DESCRIPTION

SIGNAL

A0 – A16

CE1

CE2

WE

OE

PIN NAME

Address inputs

Chip enable 1

Chip enable 2

Write enable

Output enable

SIGNAL

I/O1 – I/O8

VCC

GND

NC

PIN NAME

Data inputs and outputs

Power supply

Ground

No connection

51BV1000-2

TRUTH TABLE

CE1

CE2

WE

OE

H









L





L

H

L



L

H

H

L

L

H

H

H

NOTE:

1.  = Don’t care, L = Low, H = High

MODE

Standby

Standby

Write

Read

Output disable

I/O1 – I/O8

High impedance

High impedance

Data input

Data output

High impedance

SUPPLY CURRENT

Standby (ISB)

Standyby (ISB)

Active (ICC)

Active (ICC)

Active (ICC)

2

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