L6382D5TR データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

一致するリスト

L6382D5TR

Power management unit for microcontrolled ballast

STMicroelectronics 

Pin settings

2

Pin settings

2.1

Pin connection

Figure 3. Pin connection (top view)

PFI 1

LSI 2

HSI 3

HEI 4

PFG 5

N.C. 6

TPR 7

GND 8

LSG 9

VCC 10

20 VREF

19 CSI

18 CSO

17 HEG

16 N.C.

15 HVSU

14 N.C.

13 OUT

12 HSG

11 BOOT

L6382D5

2.2

4/21

Pin description

Table 1. Pin description

Name Pin N°

Description

1

PFI

Digital input signal to control the PFC gate driver. This pin has to be connected

to a 5V CMOS compatible signal.

2

LSI

Digital input signal to control the half-bridge low side driver. This pin has to be

connected to a 5V CMOS compatible signal.

3

HSI

Digital input signal to control the half-bridge high side driver. This pin has to be

connected to a 5V CMOS compatible signal.

4

HEI

Digital input signal to control the HEG output. This pin has to be connected to a

5V CMOS compatible signal.

PFC Driver Output. This pin must be connected to the PFC power MOSFET

gate. A resistor connected between this pin and the power MOS gate can be

5

PFG

used to reduce the peak current. An internal 10KΩ resistor toward ground

avoids spurious and undesired MOSFET turn-on

The totem pole output stage is able to drive the power MOS with a peak

current of 120mA source and 250mA sink.

6

N.C. Not connected

7

TPR

Input for two point regulator; by coupling the pin with a capacitor to a switching

circuit, it is possible to implement a charge circuit for the Vcc.

Chip ground. Current return for both the low-side gate-drive currents and the

8

GND

bias current of the IC. All of the ground connections of the bias components

should be tied to a track going to this pin and kept separate from any pulsed

current return.

Share Link: