KSZ8842-MQL データシートの表示（PDF） - Micrel
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KSZ8842-MQL Datasheet PDF : 141 Pages
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Micrel, Inc.
Pin Number
55
56
57
Pin Name
TXM2
TXP2
VDDA
58
AGND
59
NC
60
NC
61
ISET
62
AGND
63
VDDAP
64
AGND
65
X1
66
X2
67
RSTN
68
A15
69
A14
70
A13
71
A12
72
A11
73
A10
74
A9
75
A8
76
A7
77
A6
78
DGND
79
VDDIO
80
A5
81
A4
82
A3
83
A2
84
A1
85
NC
86
NC
87
BE1N
88
BE0N
89
NC
90
DGND
91
VDDC
October 2007
KSZ8842-16/32 MQL/MVL/MVLI/MBL
Type
I/O
I/O
P
Gnd
Ipu
Ipu
O
Gnd
P
Gnd
I
O
Ipu
I
I
I
I
I
I
I
I
I
I
Gnd
P
I
I
I
I
I
I
I
I
I
I
Gnd
P
Pin Function
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
1.2 analog VDD input power supply from VDDCO (pin24) through external Ferrite
bead and capacitor.
Analog ground
No connect
No connect
Set physical transmits output current.
Pull-down this pin with a 3.01K 1% resistor to ground.
Analog ground
1.2V analog VDD for PLL input power supply from VDDCO (pin24) through
external Ferrite bead and capacitor.
Analog ground
25MHz crystal or oscillator clock connection.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is a no connect.
Note: Clock requirement is ± 50ppm for either crystal or oscillator.
Hardware reset pin (active Low). This reset input is required minimum of 10ms
low after stable supply voltage 3.3V.
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
Address 8
Address 7
Address 6
Digital IO ground
3.3V digital VDDIO input power supply for IO with well decoupling capacitors.
Address 5
Address 4
Address 3
Address 2
Address 1
No Connect
No Connect
Byte Enable 1 Not, Active low for Data byte 1 enable (don’t care in 8-bit bus
mode).
Byte Enable 0 Not, Active low for Data byte 0 enable (there is an internal inverter
enabled and connected to the BE1N for 8-bit bus mode).
No Connect
Digital core ground
1.2V digital core VDD input power supply from VDDCO (pin24) through external
Ferrite bead and capacitor.
16
M9999-102207-1.9
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