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KSZ8841-PMQL(2006) データシートの表示(PDF) - Micrel

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KSZ8841-PMQL Datasheet PDF : 74 Pages
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Micrel, Inc.
KSZ8841-PMQL
Pin Description
Pin
Number
1
Pin
Name
TEST_EN
2
SCAN_EN
3
P1LED2
4
P1LED1
5
P1LED0
Type
Pin Function
I
Test Enable
For normal operation, pull-down this pin to ground.
I
Scan Test Scan Mux Enable
For normal operation, pull-down this pin to ground.
Opu Port 1 LED indicators1 defined as follows:
Opu
Opu
P1LED32
Chip Global Control Register:
CGCR bit [15,9]
[0,0] Default
[0,1]
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col 10Link/Act
P1LED0
Speed
Full duplex
Reg. CGCR bit [15,9]
P1LED32
[1,0]
[1,1]
Act
P1LED2
Link
P1LED1
Full duplex/Col —
P1LED0
Speed
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27.
6
NC
No connect
7
NC
No connect
8
NC
No connect
9
DGND
Gnd Digital ground
10
VDDIO
P
3.3V digital I/O VDD
11
NC
No connect
12
PCLK
Ipd PCI Bus Clock
This Clock provides the timing for all PCI bus phases. The rising edge defines the start
of each phase. The clock maximum frequency is 33MHz.
13
NC
No connect
14
PMEN
Opu Power Management Enable
Asserted low.
When asserted, this signal indicates that a Wake-on-LAN packet has been received in
this Ethernet MAC chip.
15
NC
No connect
16
INTRN
Opd Interrupt Request
Active Low signal to host CPU to request an interrupt when any one of the interrupt
June 2006
9
M9999-061206-1.2

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