KSZ8841-PMQL(2006) データシートの表示（PDF） - Micrel

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KSZ8841-PMQL
(Rev.:2006)

Single-Port Ethernet MAC Controller with PCI Interface

Micrel 

Micrel, Inc.

KSZ8841-PMQL

Contents

Pin Configuration .............................................................................................................................................................. 8

Pin Description .................................................................................................................................................................. 9

Functional Description ................................................................................................................................................... 14

PCI Bus Interface Unit .................................................................................................................................................. 14

PCI Bus Interface ................................................................................................................................................. 14

TXDMA Logic and TX Buffer Manager ................................................................................................................ 14

RXDMA Logic and RX Buffer Manager................................................................................................................ 14

Power Management...................................................................................................................................................... 14

Power down.......................................................................................................................................................... 14

Wake-on-LAN....................................................................................................................................................... 14

Link Change ......................................................................................................................................................... 15

Wake-up Packet ................................................................................................................................................... 15

Magic Packet........................................................................................................................................................ 15

Physical Layer Transceiver (PHY) ................................................................................................................................. 16

100BASE-TX Transmit.................................................................................................................................................. 16

100BASE-TX Receive................................................................................................................................................... 16

PLL Clock Synthesizer (Recovery) ............................................................................................................................... 16

Scrambler/De-scrambler (100BASE-TX Only).............................................................................................................. 16

10BASE-T Transmit ...................................................................................................................................................... 16

10BASE-T Receive ....................................................................................................................................................... 16

MDI/MDI-X Auto Crossover .......................................................................................................................................... 17

Straight Cable....................................................................................................................................................... 17

Crossover Cable................................................................................................................................................... 18

Auto Negotiation ........................................................................................................................................................... 18

LinkMD Cable Diagnostics ............................................................................................................................................. 20

Access........................................................................................................................................................................... 20

Usage............................................................................................................................................................................ 20

Media Access Control (MAC) and other........................................................................................................................ 20

Inter Packet Gap (IPG) ................................................................................................................................................. 20

Back-Off Algorithm........................................................................................................................................................ 20

Late Collision ................................................................................................................................................................ 20

Flow Control.................................................................................................................................................................. 20

Half-Duplex Backpressure ............................................................................................................................................ 21

Clock Generator............................................................................................................................................................ 21

EEPROM Interface ....................................................................................................................................................... 21

Loopback Support......................................................................................................................................................... 23

Host Communication ...................................................................................................................................................... 24

Host Communication Descriptor Lists and Data Buffers .............................................................................................. 24

Receive Descriptors (RDES0-RDES3) ......................................................................................................................... 24

Transmit Descriptors (TDES0-TDES3)......................................................................................................................... 26

PCI Configuration Registers .......................................................................................................................................... 28

Configuration ID Register (CFID Offset 00H) ............................................................................................................... 29

Command and Status Configuration Register (CFCS Offset 04H)............................................................................... 29

Configuration Revision Register (CFRV Offset 08H).................................................................................................... 31

Configuration Latency Timer Register (CFLT Offset 0CH)........................................................................................... 31

Configuration Base Memory Address Register (CBMA Offset 10H) ............................................................................ 31

Subsystem ID Register (CSID Offset 2CH) .................................................................................................................. 32

Capabilities Pointer Register (CCAP Offset 34H)......................................................................................................... 32

Configuration Interrupt Register (CFIT Offset 3CH) ..................................................................................................... 32

Capabilities ID Register (CCID Offset 50H).................................................................................................................. 33

Power-Management Control and Status Register (CPMC Offset 54H)........................................................................ 35

PCI Control & Status Registers ..................................................................................................................................... 36

MAC DMA Transmit Control Register (MDTXC Offset 0x0000) ................................................................................... 36

June 2006

4

M9999-061206-1.2

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