KD16903 データシートの表示（PDF） - Samsung

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コンポーネント説明

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KD16903

DATA PROCESSOR

Samsung 

KD16903

DATA PROCESSOR

- I2C Bus Interface Acknowledge

The acknowledge related clock pulse is generated by a microcontroller.

The transmitter releases the SDA line (high) during the acknowledge clock pulse. The receiver must pull down

the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock

pulse. The slave-transmitter generates negative acknowledge when read operation processes. The negative

acknowledge is generated by a master (microcontroller).

I2C Bus Interface Format-Write Operation

Chip Address

Function Address

MSB

LSB MSB

LSB MSB

S 1 0 0 0 0 0 A0 W A

A

DATA

LSB

AP

SCL

SDA

1 000 0 0 0 0

S

P

I2C Bus Interface Format-Read Operation

Chip Address

Function Address

MSB

LSB MSB

LSB MSB

S 1 0 0 0 0 0 A0 R A

A

DATA

LSB

N/

A

P

SCL

SDA

1 000 0 0 0 1

S

P

- Relationship between the I2C Bus Interface signal SCL/SDA and main clock of KD16903(CKIN)

Commands are sent from MSM to KD16903 via the I2C (SDA/SCL) bus, triggered by the input signal CKIN. To

achieve immunity towards noise, the glitch protection circuitry must be put into operation, thereby meeting the

I2C specification.

Thus CKIN should be input with the SDA/SCL.

Another issue is, at least 100 clock(CKIN) cycles are needed to execute the command completely by the

KD16903. Even as the end condition of the I2C interface is met, the MSM must supply KD16903 with CKIN, as

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