K9F2G08Q0M データシートの表示（PDF） - Samsung
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K9F2G08Q0M Datasheet PDF : 38 Pages
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K9F2G08Q0M K9F2G16Q0M
K9F2G08U0M K9F2G16U0M
Preliminary
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
2,008
Typ.
-
Max
2,048
Unit
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
AC TEST CONDITION
(K9F2GXXX0M-XCB0 :TA=0 to 70°C, K9F2GXXX0M-XIB0:TA=-40 to 85°C
K9F2GXXQ0M : Vcc=1.70V~1.95V , K9F2GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F2GXXQ0M
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL=30pF
K9F2GXXU0M
0V to Vcc
5ns
Vcc/2
1 TTL GATE and CL=50pF
CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
Test Condition
Min
CI/O
VIL=0V
-
CIN
VIN=0V
-
NOTE : Capacitance is periodically sampled and not 100% tested.
Max
10
10
Unit
pF
pF
MODE SELECTION
CLE
ALE
CE
WE
RE
WP
H
L
L
H
X
L
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
L
L
L
H
X
X
X
X
X
H
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X(1)
X
X
X
L
X
X
H
X
X
0V/VCC(2)
NOTE : 1. X can be VIL or VIH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
PRE
Mode
X
Command Input
Read Mode
X
Address Input(5clock)
X
Command Input
Write Mode
X
Address Input(5clock)
X
Data Input
X
Data Output
X
During Read(Busy)
X
During Program(Busy)
X
During Erase(Busy)
X
Write Protect
0V/VCC(2) Stand-by
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Program Time
Dummy Busy Time for Cache Program
tPROG
-
300
tCBSY
3
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
Block Erase Time
tBERS
-
2
NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in
Max
Unit
700
µs
700
µs
4
cycles
4
cycles
3
ms
10
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