ISL97642 データシートの表示（PDF） - Intersil

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ISL97642

TFT-LCD DC/DC with Integrated Amplifiers

Intersil 

ISL97642

VCDEL

IN

VREF

VBOOST

VOFF

tON

tDEL1

tDEL2

VON

VON SLICE CIRCUIT

tDEL3

NOTE: Not to scale

START-UP SEQUENCE

TIMED BY CDEL

NORMAL

FAULT

OPERATION PRESENT

FIGURE 22. START-UP SEQUENCE

Component Selection for Start-up Sequencing and

Fault Protection

The CREF capacitor is typically set at 220nF and is required

to stabilize the VREF output. The range of CREF is from

22nF to 1µF and should not be more than five times the

capacitor on CDEL to ensure correct start-up operation.

The CDEL capacitor is typically 100nF and has a usable range

from 22nF minimum to several microfarads – only limited by

the leakage in the capacitor reaching µA levels. CDEL should

be at least 1/5 of the value of CREF (see Figure 22). Note that

with 100nF on CDEL, the fault time-out will be typically 23ms

and the use of a larger/smaller value will vary this time

proportionally (e.g. 1µF will give a fault time-out period of

typically 230ms).

Fault Sequencing

The ISL97642 has an advanced fault detection system,

which protects the IC from both adjacent pin shorts during

operation and shorts on the output supplies. A high quality

layout/design of the PCB (in respect of grounding quality and

decoupling) is necessary to avoid falsely triggering the fault

16

FN6436.0

June 18, 2007

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