ISL8501 データシートの表示（PDF） - Intersil
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ISL8501 Datasheet PDF : 19 Pages
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ISL8501
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through the Equation 6:
IRMSMAX =
V-----O----U---T-
VIN
×
⎝⎛ I O
U
2
TMAX
+
--1----
12
×
⎛
⎝
-V----I-N-----–-----V----O----U---T-
L × fs
×
-V--V--O--I--UN---T-⎠⎞
2⎞
⎠
(EQ. 6)
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised wih
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 2 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at fLC and a zero at fESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ΔVOSC.
Modulator Break Frequency Equations
fLC=
---------------------1---------------------
2π x LO x CO
fESR=
---------------------1----------------------
2π x ESR x CO
(EQ. 7)
The compensation network consists of the error amplifier
(internal to the ISL8501) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180°. The following equations relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R4, C1, C2, and C3) in Figure 2. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place1st Zero Below Filter’s Double Pole (~75% fLC).
3. Place 2nd Zero at Filter’s Double Pole.
4. Place 1st Pole at the ESR Zero.
5. Place 2nd Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
fZ1
=
-----------------1------------------
2π x R4 x C2
fP1
=
---------------------------1-----------------------------
2π
x
R4
x
⎛
⎜
⎝
C-C----33-----+x-----CC----2-2-⎠⎟⎞
fZ2
=
---------------------------1---------------------------
2π x (R1 + R3) x C1
fP2
=
-----------------1------------------
2π x R3 x C1
(EQ. 8)
Figure 3 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 3. Using the guidelines from “Modulator
Break Frequency Equations” on page 17 should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at fP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 33 by adding the Modulator Gain (in dB)
to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
OSC
PWM
COMPARATOR
-
Δ VOSC
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VDDQ
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C3
C2
R4
ZFB
VDDQ
ZIN
C1 R3
R1
COMP
FB
-
+
R2
ISL8501
REFERENCE
FIGURE 32. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
17
FN6500.1
July 12, 2007
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