ISL8204M データシートの表示（PDF） - Intersil
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ISL8204M Datasheet PDF : 20 Pages
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ISL8204M, ISL8206M
The overcurrent function will trip at a peak inductor
current (IPEAK) determined by Equation 2:
IPEAK
=
2-----×-----I--S----E----T-----×----R-----S----E----T-
rDS(ON)
(EQ. 2)
where:
ISET is the internal ISET current source (21.5µA typical).
RSET is equivalent resistance between ISET and PGND
pins.
rDS(ON) is typically 15mΩ @ (VPVCC = VGS = 10V,
IDS = 15A) and 18mΩ @ (VPVCC = VGS = 4.5V,
IDS = 15A).
Note: ISL8204M, ISL8206M has integrated
4.12kΩ/2.87kΩ resistance (RSET-IN). Therefore, the
equivalent resistance of RSET can be expressed in
Equation 3:
RSET
=
-R----S----E----T-------E----X-----×----R-----S----E----T-------I-N---
RSET-EX + RSET-IN
(EQ. 3)
The scale factor of 2 doubles the trip point of the MOSFET
voltage drop, compared to the setting on the RSET
resistor. The OC trip point varies in a system mainly due
to the MOSFET rDS(ON) variations (i.e. over process,
current and temperature). To avoid overcurrent tripping
in the normal operating load range, find the RSET resistor
from Equation 3, and use the following values:
1. The maximum rDS(ON) at the highest junction
temperature
2. The minimum ISET from the “Electrical
Specifications” table on page 3.
3. Determine IPEAK for:
IP
E
A
K
>
IO
U
T
(
M
A
X
)
+
(---Δ----I--L----)
2
(EQ. 4)
where ΔIL is the output inductor ripple current. In a high
input voltage, high output voltage application, such as
20V input to 5V output, the inductor ripple becomes
excessive due to the fix internal inductor value. In such
applications, the output current will be limited from the
rating to approximately 70% of the module’s rated
current.
The relationships between the external RSET values and
the typical output current IOUT(MAX) OCP levels for
ISL8206M are as follows:
TABLE 3.
RSET
(Ω)
OPEN
OCP (A) @
VIN = 12V,
PVCC = 5V
8.1
OCP (A) @
VIN = 12V
PVCC = 12V
8.8
50kΩ
7.5
8.1
20kΩ
6.6
7.4
10kΩ
5.5
6.4
5kΩ
4.4
5.0
The range of allowable voltages detected (2 x ISET x
RSET) is 0mV to 475mV. If the voltage drop across RSET
is set too low, the following conditions may occur:
(1) Continuous OCP tripping and retry and (2) It may be
overly sensitive to system noise and inrush current
spikes, so it should be avoided. The maximum usable
setting is around 0.2V across RSET (0.4V across the
MOSFET); values above this might disable the
protection. Any voltage drop across RSET that is greater
than 0.3V (0.6V MOSFET trip point) will disable the OCP.
Note that conditions during power-up or during a retry
may look different than normal operation. During
power-up in a 12V system, the ISL8204M, ISL8206M
starts operation just above 4V; if the supply ramp is
slow, the soft-start ramp might be over well before 12V
is reached. Therefore, with low side gate drive voltages,
the rDS(ON) of the MOSFET will be higher during power-
up, effectively lowering the OCP trip. In addition, the
ripple current will likely be different at a lower input
voltage. Another factor is the digital nature of the soft-
start ramp. On each discrete voltage step, there is in
effect, a small load transient and a current spike to
charge the output capacitors. The height of the current
spike is not controlled, however, it is affected by the
step size of the output and the value of the output
capacitors, as well as the internal error amp
compensation. Therefore, it is possible to trip the
overcurrent with inrush current, in addition to the
normal load and ripple considerations.
Figure 23 shows the output response during a retry of
an output shorted to PGND. At time T0, the output has
been turned off due to sensing an overcurrent condition.
There are two internal soft-start delay cycles (T1 and
T2) to allow the MOSFETs to cool down in order to keep
the average power dissipation in retry at an acceptable
level. At time T2, the output starts a normal soft-start
cycle, and the output tries to ramp. If the short is still
applied and the current reaches the ISET trip point any
time during the soft-start ramp period, the output will
shut off and return to time T0 for another delay cycle.
The retry period is thus two dummy soft-start cycles
plus one variable (which depends on how long it takes
to trip the sensor each time). Figure 23 shows an
example where the output gets about half-way up
before shutting down; therefore, the retry (or hiccup)
time will be around 17ms. The minimum should be
nominally 13.6ms and the maximum 20.4ms. If the
short condition is finally removed, the output should
ramp up normally on the next T2 cycle.
13
FN6999.1
February 25, 2010
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