IS61LV2568_03 データシートの表示（PDF） - Integrated Silicon Solution

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IS61LV2568_03

256K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61LV2568

AC TEST CONDITIONS

Parameter

Input Pulse Level

Input Rise and Fall Times

Input and Output Timing

and Reference Levels

Output Load

Unit

0V to 3.0V

3 ns

1.5V

See Figures 1 and 2

ISSI ®

AC TEST LOADS

319 Ω

3.3V

OUTPUT

30 pF

Including

jig and

scope

353 Ω

Figure 1

319 Ω

3.3V

OUTPUT

5 pF

Including

jig and

scope

353 Ω

Figure 2

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

Symbol Parameter

tRC Read Cycle Time

tAA Address Access Time

tOHA Output Hold Time

tACE CE Access Time

tDOE OE Access Time

tLZOE(2) OE to Low-Z Output

tHZOE(2) OE to High-Z Output

tLZCE(2) CE to Low-Z Output

tHZCE(2) CE to High-Z Output

-10 ns

-12 ns

Min. Max. Min. Max.

Unit

10 —

12 —

ns

— 10

— 12

ns

3

—

3—

ns

— 10

— 12

ns

—

4

—5

ns

0

—

0—

ns

0

4

05

ns

3

—

3—

ns

0

4

05

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,

input pulse levels of 0 to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage.

Not 100% tested.

Integrated Silicon Solution, Inc. — 1-800-379-4774

5

Rev. B

02/07/03

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