IS61C25616AL データシートの表示（PDF） - Integrated Silicon Solution

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IS61C25616AL

256K x 16 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61C25616AL IS61C25616AS

IS64C25616AL IS64C25616AS

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol Parameter

-10

-12

-25

Min. Max.

Min. Max.

Min. Max.

Unit

tWC Write Cycle Time

10 —

12 —

25 —

ns

tSCE CE to Write End

7—

9—

18 —

ns

tAW Address Setup Time

7—

9—

18 —

ns

to Write End

tHA Address Hold from Write End

0—

0—

0—

ns

tSA Address Setup Time

0—

0—

0—

ns

tPWB LB, UB Valid to End of Write

7—

9—

18 —

ns

tPWE1 WE Pulse Width (OE =High)

7—

9—

15 —

ns

tPWE2 WE Pulse Width (OE=Low)

7—

9—

17 —

ns

tSD Data Setup to Write End

6—

6—

15 —

ns

tHD Data Hold from Write End

0—

0—

0—

ns

tHZWE(2) WE LOW to High-Z Output

—6

—6

— 15

ns

tLZWE(2) WE HIGH to Low-Z Output

3—

3—

5—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the write.

8

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

03/21/2008

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