CY7C0241AV-25AI データシートの表示（PDF） - Cypress Semiconductor
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CY7C0241AV-25AI Datasheet PDF : 18 Pages
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PRELIMINARY
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Characteristics Over the Operating Range[14]
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-15[1]
-20
-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
tACE[15]
Output Hold From Address Change
CE LOW to Data Valid
tDOE
tLZOE[16, 17, 18]
tHZOE[16, 17, 18]
tLZCE[16, 17, 18]
tHZCE[16, 17, 18]
tPU[18]
tPD[18]
tABE[15]
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
WRITE CYCLE
15
20
25
ns
15
20
25
ns
3
3
3
ns
15
20
25
ns
10
12
13
ns
3
3
3
ns
10
12
15
ns
3
3
3
ns
10
12
15
ns
0
0
0
ns
15
20
25
ns
15
20
25
ns
tWC
tSCE[15]
Write Cycle Time
CE LOW to Write End
15
20
25
ns
12
15
20
ns
tAW
Address Valid to Write End
12
15
20
ns
tHA
Address Hold From Write End
0
0
0
ns
tSA[15]
Address Set-Up to Write Start
0
0
0
ns
tPWE
Write Pulse Width
12
15
20
ns
tSD
Data Set-Up to Write End
10
15
15
ns
tHD
tHZWE[17, 18]
tLZWE[17, 18]
tWDD[19]
tDDD[19]
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
0
0
0
ns
10
12
15
ns
3
3
0
ns
30
45
50
ns
25
30
35
ns
Notes:
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
15. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
17. Test conditions used are Load 3.
18. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
7
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