IP100ALF データシートの表示（PDF） - Unspecified

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IP100ALF

Integrated 10/100 Ethernet MAC + PHY

Unspecified 

IP100A LF

Preliminary Data Sheet

6.2 Physical Layer

The IP100A LF supports both IEEE 802.3 100BASE-TX and 100BASE-FX signaling. The 100BASE-X

transmit logic performs 4B5B encoding/decoding, parallel to serial, and serial to parallel conversion, and

NRZ-NRZI signaling. In the case of 100BASE-TX, scrambling and MLT-3 encoding are also done before

the data is transmitted on to the media. The receive 100BASE-X circuitry, recovering data from either an

MLT-3 signal (100BASE-TX) or a PECL input (100BASE-FX), generates four bit nibbles to send to the MAC.

The Media Dependent Interface selection is done by the FFSD pin. If the FFSD pin is connected directly

to GND, the IP100A LF PHY layer is operating in TX mode. If FFSD is connected to the signal detect,

then the PHY layer is in 100BASE-FX mode.

The IP100A LF PHY also includes a full set of registers for controlling the PHY as outlined in the IEEE

802.3 specification.

6.3 On-Chip Voltage Regulator

The IP100A LF has an integrated voltage regulator for reduced system cost. The voltage regulator is used

to provide the 2.5 V power to the PCB. When used with a 2N2905 PNP transistor based circuit as shown in

Figure 2, the CTRL25 pin will regulate the current through the transistor, providing a stable 2.5 V reference.

VCC2

VCC1

IP100A LF

CTRL25

MMBT2907A

150

2.2K, 1%

Voltage

Comparator

inside IC

33

0.1u

2.0K, 1%

FIGURE 2: External PNP Transistor Based Regulator Circuit

6.4 PCI Bus Interface

The PCI Bus Interface implements the protocols and signals needed to operate the IP100A LF in a PCI

bus. The IP100A LF can be either a PCI bus master or slave. The PCI Bus Interface is also responsible

for managing the DMA interfaces and the host processors access to the IP100A LF registers. Arbitration

logic within the PCI Bus Interface block accepts bus requests from the TxDMA Logic and RxDMA Logic.

The PBI also manages interrupt generation for a host processor.

6.5 TxDMA Logic

The IP100A LF supports a multi-frame, multi-fragment DMA gather process. Descriptors representing

frames are built and linked in system memory by a host processor. The TxDMA Logic is responsible for

transferring the multi-fragment frame data from the host memory into the TxFIFO.

The TxDMA Logic monitors the amount of free space in the TxFIFO, and uses this value to decide when

to request a TxDMA. A TxDMABurstThresh register is used to delay the bus request until there is enough

free space in the TxFIFO for a long burst.

Copyright © 2004, IC Plus Corp.

14/97

March. 30, 2007

IP100A LF-DS-R17

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