IN74ACT161 データシートの表示（PDF） - Integral Corp.

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IN74ACT161

PRESETTABLE COUNTER High-Speed Silicon-Gate CMOS

Integral Corp. 

IN74ACT161

TIMING REQUIREMENTS (VCC=5.0V±10%, CL=50pF,Input tr=tf=3.0 ns)

Guaranteed Limit

Symbol

Parameter

+25° C

-40° C Unit

to +85° C

tSU Minimum Setup Time, Preset Data Inputs

9.5

to Clock (Figure 4)

11.5

ns

th Minimum Hold Time, Clock to Preset

0

Data Inputs (Figure 4)

0

ns

tSU Minimum Setup Time,Load to Clock

8.5

(Figure 4)

9.5

ns

th Minimum Hold Time, Clock to Load

-0.5

(Figure 4)

-0.5

ns

tSU Minimum Setup Time, Enable T or

5.5

Enable P to Clock (Figure 5)

6.5

ns

th Minimum Hold Time, Clock to Enable T

0

or Enable P (Figure 5)

0

ns

tw Minimum Pulse Width, Clock (Load)

3.0

(Figure 1)

3.5

ns

tw Minimum Pulse Width, Clock

3.0

(Count)(Figure 1)

3.5

ns

tw Minimum Pulse Width, Reset (Figure 2)

3.0

7.5

ns

trec Minimum Recovery Time, Reset to Clock

0

(Figure 2)

0.5

ns

5

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