IDT82P2288 データシートの表示（PDF） - Integrated Device Technology
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IDT82P2288 Datasheet PDF : 384 Pages
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IDT82P2288
2 PIN DESCRIPTION
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Name
RTIP[1]
RTIP[2]
RTIP[3]
RTIP[4]
RTIP[5]
RTIP[6]
RTIP[7]
RTIP[8]
Type Pin No.
Description
Line and System Interface
Input
C11 RTIP[1:8] / RRING[1:8]: Receive Bipolar Tip/Ring for Link 1 ~ 8
D8 These pins are the differential line receiver inputs.
D6
B4
F14
J13
L13
N14
RRING[1]
RRING[2]
RRING[3]
RRING[4]
RRING[5]
RRING[6]
RRING[7]
RRING[8]
TTIP[1]
TTIP[2]
TTIP[3]
TTIP[4]
TTIP[5]
TTIP[6]
TTIP[7]
TTIP[8]
Output
D11
D9
D5
C4
G14
H13
M13
N15
A12 TTIP[1:8] / TRING[1:8]: Transmit Bipolar Tip/Ring for Link 1 ~ 8
A8 These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A
A7 logic high on the THZ pin sets all these pins to high impedance state. When the T_HZ bit (b4, T1/J1-023H,... / b4,
A1 E1-023H,...) * is set to ‘1’, the TTIPn/TRINGn pins in the corresponding link are set to high impedance state.
E16 Besides, TTIPn/TRINGn will also be set to high impedance state by other ways (refer to Chapter 3.25 Line Driver for
J16 details).
K16
T16
TRING[1]
TRING[2]
TRING[3]
TRING[4]
TRING[5]
TRING[6]
TRING[7]
TRING[8]
RSD[1] / MRSDA[1]
RSD[2] / MRSDB[1]
RSD[3]
RSD[4]
RSD[5] / MRSDA[2]
RSD[6] / MRSDB[2]
RSD[7]
RSD[8]
High-Z
Output
A11
A9
A6
A2
F16
H16
L16
R16
P3 RSD[1:8]: Receive Side System Data for Link 1 ~ 8
R2 The processed data stream is output on these pins.
R1 In Receive Clock Master mode, the RSDn pins are updated on the active edge of the corresponding RSCKn.
P1 In Receive Clock Slave mode, determined by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSDn pins are
N2 updated on the active edge of the corresponding RSCKn or all eight RSDn pins are updated on the active edge of
M4 RSCK[1].
M2
L5 MRSDA[1:2] / MRSDB[1:2]: Multiplexed Receive Side System Data A / B for Link 1 ~ 8
In Receive Multiplexed mode, the MRSDA[1:2] pins or the MRSDB[1:2] pins are used to output the processed data
stream. Using a byte-interleaved multiplexing scheme, the MRSDA[1]/MRSDB[1] pins output the data from Link 1 to
Link 4, while the MRSDA[2]/MRSDB[2] pins output the data from Link 5 to Link 8. The data on the MRSDA[1:2]/
MRSDB[1:2] pins are updated on the active edge of the MRSCK. The data on MRSDA[1:2] is the same as the data
on MRSDB[1:2]. MRSDB[1:2] are for back-up purpose.
Note:
* The contents in the brackets indicate the position of the preceding bit and the address of the register. After the address, if the punctuation ‘,...’ is followed, this bit is in a per-link control reg-
ister and the listed address belongs to Link 1. Users can find the omitted addresses in Chapter 5. If there is no punctuation followed the address, this bit is in a global control register.
Pin Description
4
March 22, 2004
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