IDTCV152 データシートの表示（PDF） - Integrated Device Technology

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IDTCV152

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Integrated Device Technology 

IDTCV152

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS - CPU AND SRC 0.7 CURRENT MODE

DIFFERENTIAL PAIR, CONTINUED(1)

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF

Symbol

tSK3

tJCYC-CYC

Parameter

Skew, CPU(2)

Skew, SRC(2)

Jitter, Cycle to Cycle, CPU(2)

Jitter, Cycle to Cycle, SRC(2)

VT = 50%

Test Conditions

Measurement from differential waveform

NOTES:

1. SRC clock outputs run only at 100MHz.

2. This parameter is guaranteed by design, but not 100% production tested.

Min. Typ.

Max.

Unit

—

—

100

ps

—

—

250

—

—

85

ps

—

—

125

ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF

Symbol Parameter

Test Conditions

Min.

ppm

Static Error(1,2)

See Tperiod Min. - Max. values

—

TPERIOD Clock Period(2)

33.33MHz output nominal

29.991

Typ.

Max.

Unit

—

0

ppm

—

30.009

ns

33.33MHz output spread

29.991

—

30.1598

VOH

Output HIGH Voltage

IOH = -1mA

2.4

—

—

V

VOL

Output LOW Voltage

IOL = 1mA

—

—

0.55

V

IOH

Output HIGH Current

VOH at Min. = 1V

-33

—

—

mA

VOH at Max. = 3.135V

—

—

-33

IOL

Output LOW Current

VOL at Min. = 1.95V

30

—

—

mA

tR1

tF1

dT1

tSK1

tJCYC-CYC

Edge Rate(1)

Edge Rate(1)

Rise Time(1)

Fall Time(1)

Duty Cycle(1)

Skew(1)

Jitter, Cycle to Cycle(1)

VOL at Max. = 0.4V

Rising edge rate

Falling edge rate

VOL = 0.8V, VOH = 2V

VOL = 0.8V, VOH = 2V

VT = 1.5V

VT = 1.5V

VT = 1.5V

—

—

38

1

—

4

V/ns

1

—

4

V/ns

0.3

—

1.2

ns

0.3

—

1.2

ns

45

—

55

%

—

—

500

ps

—

—

500

ps

NOTES:

1. This parameter is guaranteed by design, but not 100% production tested.

2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.

11

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