IDT82V2052E データシートの表示（PDF） - Integrated Device Technology

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IDT82V2052E

DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

List of Figures

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Block Diagram ................................................................................................................. 2

IDT82V2052E TQFP80 Package Pin Assignment .......................................................... 8

E1 Waveform Template Diagram .................................................................................. 17

E1 Pulse Template Test Circuit ..................................................................................... 18

Receive Path Function Block Diagram .......................................................................... 21

Transmit/Receive Line Circuit ....................................................................................... 21

Monitoring Receive Line in Another Chip ...................................................................... 22

Monitor Transmit Line in Another Chip .......................................................................... 22

G.772 Monitoring Diagram ............................................................................................ 23

Jitter Attenuator ............................................................................................................. 24

LOS Declare and Clear ................................................................................................. 25

Analog Loopback .......................................................................................................... 28

Digital Loopback ............................................................................................................ 28

Remote Loopback ......................................................................................................... 29

Auto Report Mode ......................................................................................................... 30

Manual Report Mode ..................................................................................................... 31

TCLK Operation Flowchart ............................................................................................ 32

Serial Microcontroller Interface Function Timing ........................................................... 33

JTAG Architecture ......................................................................................................... 52

JTAG State Diagram ..................................................................................................... 55

Transmit System Interface Timing ................................................................................ 60

Receive System Interface Timing ................................................................................. 61

E1 Jitter Tolerance Performance .................................................................................. 62

E1 Jitter Transfer Performance ..................................................................................... 63

JTAG Interface Timing .................................................................................................. 64

Serial Interface Write Timing ......................................................................................... 65

Serial Interface Read Timing with SCLKE=1 ................................................................ 65

Serial Interface Read Timing with SCLKE=0 ................................................................ 65

Non-Multiplexed Motorola Read Timing ........................................................................ 66

Non-Multiplexed Motorola Write Timing ........................................................................ 67

Non-Multiplexed Intel Read Timing ............................................................................... 68

Non-Multiplexed Intel Write Timing ............................................................................... 69

List of Figures

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December 12, 2005

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