IDT82V2048 データシートの表示（PDF） - Integrated Device Technology

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IDT82V2048

OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL TEMPERATURE RANGES

POWER DRIVER FAILURE MONITOR

An internal power Driver Failure Monitor (DFM), parallelly connected

with TTIPn and TRINGn, can detect short circuit failure in the secondary

side of transformer. This feature is available only in host mode with no

transmit series resistors, i.e. in T1 mode with VDDT is 3.3V.

Bit SCPB in Register GCF decides whether the output driver short-

circuit protection is enabled. (Refer to Programming Information).

When it is enabled, the max driver’s output current is limited to 150mA.

LINE PROTECTION

In transmit side, the Schottky diodes D1~D4 are required to protect

the line driver and improve the design robustness. In receive side, the

series resistors of 1kΩ are used to protect the receiver against current

surges coupled in the device. It does not affect the receiver sensitivity,

since the receiver impedance is as high as 120kΩ typically.

HITLESS PROTECTION SWITCHING (HPS)

The IDT82V2048 tranceivers include an output driver tristatability

feature for T1/E1 redundancy applications. This feature greatly reduces

the cost of implementing redundancy protection by eliminating external

relays. Details of HPS will be described in relative Application Note.

RESET

Writing register RS can cause software reset by initiating about 1µs

reset cycle. This operation set all the registers to their default value.

POWER UP

During power up, an internal reset signal sets all the registers to de-

fault values. This procedure takes at least 2 machine cycles.

POWER DOWN

Each transmitter channel will be power down by pulling pin TCLKn to

low for more than 64 MCLK cycles (if MCLK is available) or about 30us

(when MCLK is not availabe). Each transmitter channel will also be

power down by setting bit TPDNn in e-TPDN to 1.

All the receivers will power down when MCLK is Low. When MCLK is

clocked or High, setting bit RPDNn in e-RPDN to ‘1’ will configure the

corresponding receiver to power down.

INTERFACE WITH 5V LOGIC

The IDT82V2048 can interface directly with 5V TTL family devices.

The internal input pads are tolerant to 5V output from TTL and CMOS

family devices.

LOOPBACK MODE

The device provides five different diagnostic loopback configurations:

Digital Loopback, Analog Loopback, Remote Loopback, Dual Loopback

and Inband Loopback. In host mode, these functions are implemented

by programming the registers DLB, ALB, RLB or Inband Loopback reg-

ister group. In hardware mode, only analog loopback and remote

loopback can be selected by pulling pin LPn to High and Low respec-

tively.

RCLKn, RDn/RDPn and CVn/RDNn. The data to be transmitted are still

output on TTIPn and TRINGn while the data received on RTIPn and

RRINGn are ignored. The Loss Detector is still in use. Figure-13 shows

the process.

Analog Loopback

By programming the bits of ALB register or pulling pin LPn to High,

each channel of the device can be set in Analog Loopback. In this

configuration, the data to be transmitted output from the line driver are

internally looped back to the slicer and peak detector in the receive path

and output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be

transmitted are still output on TTIPn and TRINGn while the data

received on RTIPn and RRINGn are ignored. The Loss Detector is still in

use. Figure-14 shows the process.

The TTIPn and RTIPn, TRINGn and RRINGn cannot be connected

directly to do the external analog loopback test. Line impedance loading

is required to connduct the external analog loopback test.

Remote Loopback

By programming the bits of RLB register or pulling pin LPn to Low,

each channel of the device can be set in Remote Loopback. In this

configuration, the data and clock recovered by the Clock and Data

Recovery circuits are looped to waveform shaper and output on TTIPn

and TRINGn. The jitter attenuator is also included in loopback when

enabled in the transmit or receive path. The received data and clock are

still output on RCLKn, RDn/RDPn and CVn/RDNn while the data to be

transmitted on TCLKn, TDn/TDPn and BPVIn/TDNn are ignored. The

Loss Detector is still in use. Figure-15 shows the process.

Dual Loopback

Dual Loopback mode is set by setting both bit DLBn in register DLB

and bit RLBn in register RLB to ‘1’. In this configuration, after passing

the encoder, the data and clock to be transmitted are looped back to

decoder directly and output on RCLKn, RDn/RDPn and CVn/RDNn. The

recovered data from RTIPn and RRINGn are looped back to waveform

shaper through JA (if selected) and output on TTIPn and TRINGn. The

Loss Detector is still in use. Figure-16 shows the process.

Transmit All Ones

In hardware mode, the TAOS mode is set by pulling TCLKn High for

more than 16 MCLK cycles. In host mode, TAOS mode is set by pro-

gramming register TAO. In addition, automatic TAO signals are inserted

by setting register ATAO when Loss of Signal occurs. Note that the

TAOS generator adopts MCLK as a timing reference. In order to assure

that the output frequency is within specification limits, MCLK must have

the applicable stability.

This TAOS mode and Digital Loopback or Analog Loopback can be

configured simultaneously.

Figure-17 shows their process.

Digital Loopback

By programming the bits of register DLB, each channel of the device

can be set in Local Digital Loopback. In this configuration, the data and

clock to be transmitted, after passing the encoder, is looped back to jitter

attenuator (if enabled) and decoder in the receive path, then output on

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