IDT82V2048 データシートの表示（PDF） - Integrated Device Technology
部品番号
コンポーネント説明
メーカー
IDT82V2048 Datasheet PDF : 61 Pages
| |||
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
TABLE - 1a. SYSTEM INTERFACE CONFIGURATION (Hardware Mode)
INDUSTRIAL TEMPERATURE RANGES
MCLK
clocked
clocked
H
L
TDNn
H ( 16 MCLK)
pulse
pulse
pulse
Hardware Mode
Interface
Single Rail mode 1
Dual Rail with Clock Recovery
Receive just slice the incoming data. Transmit is determined by the status of TCLKn.
Receive is power down. Transmit is determined by the status of TCLKn.
TABLE - 1b. SYSTEM INTERFACE CONFIGURATION (Host Mode)
MCLK
clocked
clocked
clocked
clocked
H
L
TDNn
H
pulse
pulse
pulse
pulse
pulse
CRSn in e-CRS
0
0
0
1
-
-
Host Mode
SINGn in e-SING
0
1
0
0
-
-
Interface
Single Rail mode 1
Single Rail mode 2
Dual Rail with Clock Recovery
Dual Rail with Data Recovery
Receive just slice the incoming data.
Transmit is determined by the status of TCLKn.
Receive is power down.
Transmit is determined by the status of TCLKn.
TABLE - 2.ACTIVE CLOCK EDGEAND ACTIVE LEVEL
Pin CLKE
Low
RD/RDP and CV/RDN
Clock recovery
Slicer output
RCLK
Active High Active Low
SDO
SCLK Active High
High
RCLK
Active High Active High
SCLK Active High
CLOCK EDGES
The active edge of RCLK and SCLK(serial interface clock) are also
selectable. If pin CLKE is Low, the active edge of RCLK is the rising
edge, as for SCLK, that is falling edge. On the contrary, if CLKE is High,
the active edge of RCLK is the falling edge and that of SCLK is rising
edge. Pins RDn/RDPn, CVn/RDNn and SDO are always active high, and
those output signals are valid on the active edge of RCLK and SCLK
respectively. See Table-2 for details. However, in dual rail mode without
clock recovery, pin CLKE is used to set the active level for RDPn/RDNn
raw slicing output: High for active high polarity and Low for active low. It
should be noted that data on pin SDI are always active high and is
sampled on the rising edge of SCLK. The data on pin TD/TDP or BPVI/
TDN are also always active high but is sampled on the falling edge of
TCLK, despite the level on CLKE.
RECEIVER
In receive path, the line signals couple into RRINGn and RTIPn via a
transformer and are converted into RZ digital pulses by a data slicer.
Adaptation for attenuation is achieved using an integral peak detector
that sets the slicing levels. Clock and data are recovered from the
received RZ digital pulses by a digital phase-locked loop that provides
excellent jitter accommodation. After passing through the selectable jitter
attenuator, the recovered data are decoded using B8ZS/HDB3 or AMI
line code rules and clocked out of pin RDn in single rail mode, or
presented on RDPn/RDNn in an undecoded dual rail NRZ format. Loss
of signal, alarm indication signal, line code violations and excessive zero
are detected. The presence of programmable inband loopback codes
are also detected. These various changes in status may be enabled to
generate interrupts.
Peak Detector and Slicer
The slicer determines the presence and polarity of the received
pulses. In data recovery mode, the raw positive slicer output appears on
14
Share Link: 