IDT82V2048(2010) データシートの表示（PDF） - Integrated Device Technology

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IDT82V2048
(Rev.:2010)

OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL TEMPERATURE RANGES

2 FUNCTIONAL DESCRIPTION

2.1 OVERVIEW

The IDT82V2048 is a fully integrated octal short-haul line interface

unit, which contains eight transmit and receive channels for use in either

T1 or E1 applications. The receiver performs clock and data recovery.

As an option, the raw sliced data (no retiming) can be output to the

system. Transmit equalization is implemented with low-impedance

output drivers that provide shaped waveforms to the transformer, guar-

anteeing template conformance. A selectable jitter attenuator may be

placed in the receive path or the transmit path. Moreover, multiple

testing functions, such as error detection, loopback and JTAG boundary

scan are also provided. The device is optimized for flexible software

control through a serial or parallel host mode interface. Hardware control

is also available. Figure-1 on page 1 shows one of the eight identical

channels operation.

2.2 T1/E1 MODE SELECTION

T1/E1 mode selection configures the device globally. In Hardware

Mode, the template selection pins TS[2:0], determine whether the opera-

tion mode is T1 or E1 (see Table-9 on page 19). In Software Mode, the

register TS determines whether the operation mode is T1 or E1.

2.2.1 SYSTEM INTERFACE

The system interface of each channel can be configured to operate

in different modes:

1. Single rail interface with clock recovery.

2. Dual rail interface with clock recovery.

3. Dual rail interface with data recovery (that is, with raw data

slicing only and without clock recovery).

Each signal pin on system side has multiple functions depending on

which operation mode the device is in.

The Dual Rail interface consists of TDPn1, TDNn, TCLKn, RDPn,

RDNn and RCLKn. Data transmitted from TDPn and TDNn appears on

TTIPn and TRINGn at the line interface; data received from the RTIPn

and RRINGn at the line interface are transferred to RDPn and RDNn

while the recovered clock extracting from the received data stream

outputs on RCLKn. In Dual Rail operation, the clock/data recovery mode

is selectable. Dual Rail interface with clock recovery shown in Figure-4

is a default configuration mode. Dual Rail interface with data recovery is

shown in Figure-5. Pin RDPn and RDNn, are raw RZ slice outputs and

internally connected to an EXOR which is fed to the RCLKn output for

external clock recovery applications.

In Single Rail mode, data transmitted from TDn appears on TTIPn

and TRINGn at the line interface. Data received from the RTIPn and

RRINGn at the line interface appears on RDn while the recovered clock

extracting from the received data stream outputs on RCLKn. When the

device is in single rail interface, the selectable AMI or B8ZS/HDB3 line

encoder/decoder is available and any code violation in the received data

will be indicated at the CVn pin. The Single Rail mode has 2 sub-modes:

Single Rail Mode 1 and Single Rail Mode 2. Single Rail Mode 1, whose

interface is composed of TDn, TCLKn, RDn, CVn and RCLKn, is real-

ized by pulling pin TDNn high for more than 16 consecutive TCLK

cycles. Single Rail Mode 2, whose interface is composed of TDn,

TCLKn, RDn, CVn, RCLKn and BPVIn, is realized by setting bit CRS in

register e-CRS2 and bit SING in register e-SING. The difference

between them is that, in the latter mode bipolar violation can be inserted

via pin BPVIn if AMI line code is selected.

The configuration of the Hardware Mode System Interface is summa-

rized in Table-2. The configuration of the Host Mode System Interface is

summarized in Table-3.

1. The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels.

2. The first letter ‘e-’ indicates expanded register.

RTIPn

RRINGn

Slicer

LOS

Detector

CLK&Data

Recovery

(DPLL)

One of Eight Identical Channels

Jitter

Attenuator

B8ZS/

HDB3/AMI

Decoder

TTIPn

TRINGn

Peak

Detector

Line

Driver

Waveform

Shaper

Jitter

Attenuator

B8ZS/

HDB3/AMI

Encoder

Transmit

All Ones

Note: The grey blocks are bypassed and the dotted blocks are selectable.

Figure-4 Dual Rail Interface with Clock Recovery

LOSn

RCLKn

RDPn

RDNn

TCLKn

TDPn

TDNn

12

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