IDT72V36103 データシートの表示（PDF） - Integrated Device Technology

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IDT72V36103

3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36

Integrated Device Technology 

IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)

Symbol Parameter

IDT72V3683L10 IDT72V3683L15

IDT72V3693L10 IDT72V3693L15

IDT72V36103L10 IDT72V36103L15

Min. Max. Min. Max. Unit

fS

Clock Frequency, CLKA or CLKB

— 100

— 66.7 MHz

tCLK

Clock Cycle Time, CLKA or CLKB

10

—

15

—

ns

tCLKH

Pulse Duration, CLKA or CLKB HIGH

4.5

—

6

—

ns

tCLKL

Pulse Duration, CLKA and CLKB LOW

4.5

—

6

—

ns

tDS

Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑

tENS1

Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑

3

—

4

—

ns

4

—

4.5

—

ns

tENS2

tRSTS

tFSS

Setup Time, ENA, and MBA before CLKA↑; ENB and MBB before CLKB↑

Setup Time, RS1 or PRS LOW before CLKA↑ or CLKB↑(1)

Setup Time, FS0, FS1 and FS2 before RS1 HIGH

3

—

4.5

—

ns

5

—

5

—

ns

7.5

—

7.5

—

ns

tBES

Setup Time, BE/FWFT before RS1 HIGH

7.5

—

7.5

—

ns

tSDS

tSENS

Setup Time, FS0/SD before CLKA↑

Setup Time, FS1/SENbefore CLKA↑

3

—

3

—

4

—

ns

4

—

ns

tFWS

Setup Time, FWFT before CLKA↑

0

—

0

—

ns

tDH

tRTMS

Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑

Setup Time, RTM before RT1; RTM before RT2

0.5

—

5

—

1

—

ns

5

—

ns

tENH

Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB

0.5

—

after CLKB↑

tRSTH

Hold Time, RS1 or PRS LOW after CLKA↑ or CLKB↑(1)

4

—

tFSH

Hold Time, FS0, FS1 and FS2 after RS1 HIGH

2

—

tBEH

Hold Time, BE/FWFT after RS1 HIGH

2

—

1

—

ns

4

—

ns

2

—

ns

2

—

ns

tSDH

tSENH

tSPH

tRTMH

tSKEW1(2)

tSKEW2(2,3)

Hold Time, FS0/SD after CLKA↑

Hold Time, FS1/SEN HIGH after CLKA↑

Hold Time, FS1/SEN HIGH after RS1 HIGH

Hold Time, RTM after RT1; RTM after RT2

Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR

Skew Time between CLKA↑ and CLKB↑ for AE and AF

0.5

—

1

—

ns

0.5

—

1

—

ns

2

—

2

—

ns

5

—

5

—

ns

5

—

7.5

—

ns

12

—

12

—

ns

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

3. Design simulated, not tested.

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