71V016S15 データシートの表示（PDF） - Integrated Device Technology

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71V016S15

3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)

Integrated Device Technology 

IDT71V016, 3.3V CMOS Static RAM

1 Meg (64K x 16-Bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)

tWC

ADDRESS

tAW

CS

tAS

tCW (2)

tBW

BHE , BLE

tWP

tWR

WE

E DATAOUT

IN NC DATAIN

tDH

tDW

DATAIN VALID

3211 drw 10

RT CE 16SANS Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)

PA ES V0 SIG ADDRESS

L 71 DE CS

SO ER W BHE, BLE

B RD NE WE

tWC

tAW

tAS

tCW (2)

tBW

tWP

tWR

O OFOR DATAOUT

tDW

tDH

DATAIN

DATAIN VALID

3211 drw 11

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6.472

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