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IDT71321 データシートの表示(PDF) - Integrated Device Technology

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IDT71321
IDT
Integrated Device Technology IDT
IDT71321 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE (3)
tACE
CE
tAOE (4)
OE
(1)
tLZ
DATAOUT
ICC
CURRENT
ISS
tLZ (1)
tPU
50%
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition Low.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
COMMERCIAL TEMPERATURE RANGE
tHZ (2)
tHZ(2)
VALID DATA
tPD(4)
50%
2691 drw 07
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
71321X20 71321X25 71321X35 71321X55 71321X100
Symbol
Parameter
71421X25 71421X35 71421X55 71421X100
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC
Write Cycle Time(2)
20 — 25 — 35 — 55 — 100 —
ns
tEW
Chip Enable to End of Write
15 — 20 — 30 — 40 —
90 —
ns
tAW
Address Valid to End of Write
15 — 20 — 30 — 40 —
90 —
ns
tAS
Address Set-up Time
tWP
Write Pulse Width(3)
0—
0—
0—
0—
0—
ns
15 — 15 — 25 — 30 —
55 —
ns
tWR
Write Recovery Time
0—
0—
0—
0—
0—
ns
tDW
Data Valid to End of Write
tHZ
Output High-Z Time(1)
10 — 12 — 15 — 20 —
40 —
ns
— 10 — 10 — 15 — 25
— 40
ns
tDH
Data Hold Time
tWZ
Write Enabled to Output in High-Z(1)
tOW
Output Active From End of Write(1)
0—
0—
0—
0—
0—
ns
— 10 — 10 — 15 — 30
— 40
ns
0—
0—
0—
0—
0—
ns
NOTES:
2692 tbl 10
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
W 2. For Master/Slave combination, tWC = tBAA + tWP, since R/ = VIL must occur after tBAA .
3. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
4. “X” in part numbers indicates power rating (SA or LA).
6.03
6

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