IDT7132LA55F データシートの表示（PDF） - Integrated Device Technology

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IDT7132LA55F

HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS

Integrated Device Technology 

IDT7132SA/LA and IDT 7142SA/LA

High Speed 2K x 8 Dual Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)

tWC

ADDR"A"

MATCH

tWP

R/W"A"

tDW

tDH

DATAIN"A"

tAPS(1)

VALID

ADDR"B"

BUSY"B"

tBAA

MATCH

tBDA

tWDD

tBDD

DATAOUT"B"

VALID

tDDD

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

2692 drw 11

Timing Waveform of Write with BUSY(4)

tWP

R/W"A"

BUSY"B"

tWB(3)

R/W"B"

tWH(1)

,

(2)

2692 drw 12

NOTES:

1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB applies only to the slave version (IDT7142).

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

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