IDT71024 データシートの表示（PDF） - Integrated Device Technology

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IDT71024

CMOS STATIC RAM 1 MEG (128K x 8-BIT)

Integrated Device Technology 

IDT71024

CMOS STATIC RAM 1MEG (128K x 8-BIT)

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 5, 7)

ADDRESS

CS1

tWC

tAW

tCW

CS2

WE

DATAOUT

DATAIN

tAS

(4)

tWHZ (6)

tWP (7)

tWR (3)

tOW (6)

HIGH IMPEDANCE

tDH

tDW

DATAIN VALID

tCHZ (6)

(4)

2964 drw 09

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS1 AND CS2 CONTROLLED TIMING)(1, 2, 5)

ADDRESS

CS1

tWC

tAW

CS2

tAS

WE

DATAIN

tCW

tWR (3)

tDW

tDH

DATAIN VALID

2964 drw 10

NOTES:

1. WE must be HIGH, CS1 must be HIGH, or CS2 must be LOW during all address transitions.

2. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.

3. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance

state. CS1 and CS2 must both be active during the tCW write period.

6. Transition is measured ±200mV from steady state.

7. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to

turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the

minimum write pulse is the specified tWP.

7

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