IDT70P35L25PF データシートの表示（PDF） - Integrated Device Technology
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IDT70P35L25PF
Integrated Device Technology
IDT70P35L25PF Datasheet PDF : 22 Pages
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IDT70P35/34L (IDT70T25/24L)
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
ADVANCED
Industrial and Commercial Temperature Ranges
IDT70P35/34 Pin Configurations(cont'd) (1,2,3,4)
IDT70P35/34BF
BF100(5)
12/16/03
A1
A2
A6R A9R
A3
A4
A12R(1) CER
100-Pin fpBGA
Top View(6)
A5
A6
A7
VSS VSS VSS
A8
A9
A10
I/O13R I/O10R I/O7R
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
NC NC A8R A10R SEMR R/WR OER I/O12R I/O9R I/O6R
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
A3R A4R A5R A7R UBR I/O16R I/O15R I/O11R I/O8R I/O3R
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
A1R INTR A2R NC A11R LBR I/O14R I/O17R I/O5R I/O1R
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
M/S BUSYR A0R A1L VSS VSS I/O4R I/O2R I/O0R VDD
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
VSS BUSYL A0L NC VDD VSS VDD I/O14L I/O15L I/O16L
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
, INTL A3L A6L NC VSS I/O3L NC I/O12L VSS I/O13L
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
A2L A5L A10L LBL CEL I/O1L I/O7L I/O8L I/O17L I/O11L
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
A4L A8L A11L SEML R/WL OEL I/O4L I/O6L VSS I/O10L
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
A7L A9L A12L(1) UBL VDD VDD I/O0L I/O2L I/O5L I/O9L
NOTES:
1. A12 is a NC for IDT70P34.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
5683 drw 03
6.342
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