IDT7028L(2009) データシートの表示（PDF） - Integrated Device Technology

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IDT7028L
(Rev.:2009)

HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

HIGH-SPEED

64K x 16 DUAL-PORT

STATIC RAM

IDT7028L

Features

◆ True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆ High-speed access

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

◆ Low-power operation

– IDT7028L

Active: 1W (typ.)

Standby: 1mW (typ.)

◆ Dual chip enables allow for depth expansion without

external logic

◆ IDT7028 easily expands data bus width to 32 bits or

more using the Master/Slave select when cascading more

than one device

Functional Block Diagram

R/WL

UBL

CE0L

CE1L

OEL

LBL

◆ M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

◆ Interrupt Flag

◆ On-chip port arbitration logic

◆ Full on-chip hardware support of semaphore signaling

between ports

◆ Fully asynchronous operation from either port

◆ Separate upper-byte and lower-byte controls for multi-

plexed bus and bus matching compatibility

◆ TTL-compatible, single 5V (±10%) power supply

◆ Available in a 100-pin TQFP

◆ Industrial temperature range (–40°C to +85°C) is available

for selected speeds

R/WR

UBR

CE0R

CE1R

OER

LBR

I/O 8-15L

I/O 0-7L

BUSYL(1,2)

I/O

Control

I/O

Control

A15L

A0L

Address

Decoder

16

64Kx16

MEMORY

ARRAY

7028

16

CE0L

CE1L

OEL

R/WL

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

SEML

NOTES:

INT

(2)

L

M/S(2)

1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

1

©2009 Integrated Device Technology, Inc.

Address

Decoder

I/O8-15R

I/O0-7R

BUSYR(1,2)

A15R

A0R

CE0R

CE1R

OER

R/WR

SEMR

INTR (2)

4836 drw 01

JANUARY 2009

DSC-4836/4

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