IDT54FCT139TSOB データシートの表示（PDF） - Integrated Device Technology

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IDT54FCT139TSOB

FAST CMOS DUAL 1-OF-4 DECODER WITH ENABLE

Integrated Device Technology 

IDT54/74FCT139T/AT/CT

FAST CMOS DUAL 1-OF-4 DECODER WITH ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

V CC

VIN

Pulse

Generator

D.U.T.

RT

VOUT

50pF

CL

500Ω

500Ω

SWITCH POSITION

Test

Switch

7.0V

Open Drain

Disable Low

Closed

Enable Low

All Other Tests

Open

DEFINITIONS:

2566 lnk 08

CL= Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

2566 drw 04

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

DATA

INPUT

tSU

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

tSU

ETC.

tH

tREM

tH

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

tPLH

tPHL

OUTPUT

tPLH

tPHL

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V

0V

LOW-HIGH-LOW

3V

PULSE

1.5V

0V

tW

3V

1.5V

0V

HIGH-LOW-HIGH

PULSE

3V

1.5V

0V

2566 drw 05

ENABLE AND DISABLE TIMES

1.5V

1.5V

2566 drw 06

3V

1.5V

0V

VOH

1.5V

VOL

3V

1.5V

0V

2566 drw 07

ENABLE

DISABLE

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

tPZL

SWITCH

CLOSED

tPZH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

3V

1.5V

0V

tPLZ

3.5V

3.5V

1.5V

tPHZ

0.3V VOL

1.5V

0.3V VOH

0V

0V

NOTES:

2566 drw 08

1. Diagram shown for input Control Enable-LOW and input Control Disable-

HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

6.4

4

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