ICS94236 データシートの表示（PDF） - Integrated Circuit Systems
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ICS94236 Datasheet PDF : 17 Pages
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ICS94236
General Description
The ICS94236 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
The ICS94236 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Pin Descriptions
PIN NUMBER
1
2
3,9,16,22,
33,39,45, 47
4
PIN NAME
VDDREF
REF0
GND
X1
5
X2
6,14
VDDPCI
PCICLK_F
7
FS4 2
FS3 2
8
PCICLK0
SEL24_48#1, 2
10
PCICLK1
TYPE
PWR
OUT
DESCRIPTION
REF, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
PWR Ground
IN
OUT
PWR
OUT
IN
IN
OUT
IN
OUT
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Supply for PCICLK_F and PCICLK, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock output
Logic input to select 24 or 48MHz for pin 25 output
PCI clock output.
11, 12, 13
PCICLK(2:4)
OUT PCI clock outputs.
15
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
19,30,36
BUFFER IN
SDRAM (11:0)
VDDSDR
IN Input to Fanout Buffers for SDRAM outputs.
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
PWR Supply for SDRAM nominal 3.3V.
23
SDATA
IN Data input for I2C serial input, 5V tolerant input
24
SCLK
IN Clock input of I2C input, 5V tolerant input
24_48MHz
OUT 24MHz/48MHz clock output
25
FS1 2
IN Frequency select pin. Latched Input.
48MHz
26
FS0 2
OUT 48MHz output clock
IN Frequency select pin. Latched Input
27
VDD48
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
40
SDRAM_OUT
OUT Reference clock for SDRAM zero delay buffer
41
PD#1, 2
IN Powers down chip, active low
42
VDDCPU
PWR Supply for CPU clock 3.3V
43
CPUCLKT0
OUT
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
44
CPUCLKC0
OUT
"Complementory" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up.
46
CPUCLK
OUT 3.3V CPU clock output powered by VDDCPU
REF1
48
FS22
OUT 14.318 MHz reference clock.
IN Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0451A—01/10/03
2
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