ICS9250-29 データシートの表示（PDF） - Integrated Circuit Systems

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ICS9250-29

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Integrated Circuit Systems 

Power Down Waveform

ICS9250-29

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the

output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

Maximum Allowed Current

Solano

Condition

Powerdown Mode

(PWRDWN# = 0)

Full Active 66MHz

FS(1:0) = 00

Full Active 100MHz

FS(1:0) = 01

Full Active 133MHz

FS(1:0) = 11

Full Active 133MHz

FS(1:0) = 10

Max 2.5V supply consumption Max 3.3V supply consumption

Max discrete cap loads,

Max discrete cap loads,

Vddq2 = 2.625V

Vddq3 = 3.465V

All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND

2mA

2mA

35mA

440mA

50mA

430mA

60mA

440mA

60mA

500mA

Clock Enable Configuration

PD# CPUCLK SDRAM IOAPIC

0

LOW

LOW LOW

1

ON

ON

ON

3V66

LOW

ON

PCICLK

REF,

48MHz

Osc VCOs

LOW LOW OFF OFF

ON

ON ON ON

3

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