ICS9250YF-23 データシートの表示（PDF） - Integrated Circuit Systems
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ICS9250YF-23
Integrated Circuit Systems
ICS9250YF-23 Datasheet PDF : 15 Pages
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ICS9250-23
General Description
The ICS9250-23 is a single chip clock solution for desktop designs using the 810/810E style chipset. It provides all necessary
clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-23
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN
NUMBER
1
2, 9, 10, 18, 25,
32, 33, 37, 45
PIN NAME
REF1
VDD
3
X1
4
X2
5, 6, 14, 21,
28, 29, 36,
41, 49
8, 7
11
12
20, 19, 17, 16,
15, 13
GND
3V66 [1:0]
PCICLK01
FS0
PCICLK11
FS1
PCICLK [7:2]
22
PD#
23
SCLK
24
SDATA
48MHz
34
FS3
35
38
26, 27, 30, 31,
39, 40, 42, 43,
44, 46, 47, 48
50
FS2
24MHz
SDRAM_F
SDRAM [11:0]
GNDL
51, 52
CPUCLK [1:0]
53, 55
54
56
VDDL
IOAPIC
FS4
REF01
TYPE
DESCRIPTION
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply.
IN
OUT
Crystal input, has internal load cap (33pF) and feedback
resistor from X2.
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply.
OUT
OUT
IN
OUT
IN
3.3V Fixed 66MHz clock outputs for HUB.
3.3V PCI clock outputs, with Synchronous CPUCLKS.
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock outputs, with Synchronous CPUCLKS.
Logic input frequency select bit. Input latched at power on.
OUT
IN
IN
I/O
OUT
IN
IN
OUT
OUT
OUT
3.3V PCI clock outputs, with Synchronous CPUCLKS.
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
Clock input of I2C input.
Data pin for I2C circuitry 5V tolerant.
3.3V Fixed 48MHz clock output for USB.
Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
3.3V fixed 24MHz output.
3.3V free running 100MHz SDRAM not affected by I2C.
3.3V output running 100MHz. All SDRAM outputs can be turned off
through I2C.
PWR
OUT
PWR
OUT
IN
OUT
Ground for 2.5V power supply for CPU & APIC.
2.5V Host bus clock output. Output frequency derived from FS pins.
2.5V power suypply for CPU, IOAPIC.
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
Third party brands and names are the property of their respective owners.
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