AV9148F-53 データシートの表示（PDF） - Integrated Circuit Systems

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AV9148F-53

Frequency Generator & Integrated Buffers for Mother Boards

Integrated Circuit Systems 

ICS9148 - 53

AGP_STOP# Timing Diagram

AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP (0:1) clocks. for low power

operation. AGP_STOP# is synchronized by the ICS9148-53. The AGP2 clock is free-running and is not affected by AGP_STOP#.

All other clocks will continue to run while the AGPCLKs are disabled. The AGPCLKs will always be stopped in a low state and

start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and

AGPCLK off latency is less than 4 AGPCLKs. This function is available only with MODE pin latched low.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. AGP_STOP# is an asynchronous input and metastable conditions may exist.

This signal is synchronized to the CPUCLKs inside the ICS9148-53.

3. All other clocks continue to run undisturbed.

4. PD# and PCI_STOP# are shown in a high (true) state.

5. Only applies if MODE pin latched 0 at power up.

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