ICS8521BYI データシートの表示（PDF） - Integrated Circuit Systems
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ICS8521BYI Datasheet PDF : 14 Pages
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8521I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 4A to 4D show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3
R4
125
125
3.3V
CLK
nCLK HiPerClockS
Input
R1
R2
84
84
3.3V
Zo = 50 Ohm
LVDS_Driv er
R1
100
Zo = 50 Ohm
3.3V
CLK
nCLK Receiv er
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V LVPECL
3.3V
Zo = 50 Ohm
R3
R4
84
84
C1
Zo = 50 Ohm
C2
R5
100 - 200
R6
100 - 200
R1
R2
125 125
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
8521BYI
www.icst.com/products/hiperclocks.html
9
REV. A NOVEMBER 17, 2005
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