HYS 64/72V64220GU
SDRAM-Modules
AC Characteristics (cont’d) 1), 2)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit Note
-7
-7.5
-8
PC133-222 PC133-333 PC100-222
min. max min. max. min. max.
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
Read Cycle
Data Out Hold Time
Data Out to Low Impedance
Data Out to High Impedance
DQM Data Out Disable Latency
Write Cycle
Data Input to Precharge
(write recovery)
DQM Write Mask Latency
tREF 64 –
–
64 –
64 ms 6)
tSREX –
1
1
–
1
–
CLK 8)
tOH
3
–
3
–
3
–
ns 2)
tLZ
0
–
0
–
0
–
ns –
tHZ
3
7
3
7
3
8
ns 9)
tDQZ –
2
–
2
–
2
CLK –
tWR
2
–
2
–
2
–
CLK –
tDQW 0
–
0
–
0
–
CLK –
Notes
4. All AC characteristics are shown on SDRAM component level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
5. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
6. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter.
7. Rated at 1.4 V
8. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
9. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
10.Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
INFINEON Technologies
8
9.01