HT0610 データシートの表示（PDF） - Holtek Semiconductor

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HT0610

33 x 120 LCD Driver

Holtek Semiconductor 

Block Diagram

IB P IC O N 0 ~ IC O N 3 S E G 0 ~ S E G 1 1 9 C O M 0 ~ C O M 3 2

S ta tic Ic o n

C o n tr o l C ir c u it

H ig h V o lta g e C e ll L e v e l S h ifte r

Level

S e le c to r

O SC1

O SC2

T im in g G e n e r a to r

fo r D is p la y

VDD

VSS

1 5 5 B its L a tc h

( 3 3 B its & 1 2 0 B its )

BG DRAM

1 2 0 ´ 3 3 B its

L C D D r iv in g

V o lta g e G e n e r a to r

D o u b le r & T r ip le r

V o lta g e R e g u la to r ,

V o lta g e D iv id e r ,

C o n tr a s t C o n tr o l,

T e m p e ra tu re

C o m p e n s a tio n

C ir c u it

C o m m a n d D e c o d e r C ir c u it

HT0610

V LL2

V LL6

VCCA1

VR

VF

C 2P

C 2N

C 1P

C 1N

DUM 2

DUM 1

C+

C-

VDDA

C o m m a n d In te rfa c e

P a r a lle l In te r fa c e

C S (C L K ) D C O M R E S C E

RW

D 0~D 7

Operation of LCD Driver

Description of block diagram module

Block

Description

This module determines whether the input data is interpreted as data or command.

Data is directed to this module based upon the input of the DCOM pin. If DCOM High,

then data is written to BGDRAM ( Built-in Graphic Display data RAM) . DCOM pin Low

Command Decoder

Command Interface

and

indicates that the input at D0~D7 is interpreted as a Command.

CE is the master chip selection signal . A High input enable the input lines ready to sam-

ple signals.

RES pin of same function as Power On Reset (POR). Once RES received the reset sig-

nal, all internal circuitry will back to its initial status. Refer to Command Description

section for more information.

Parallel Interface

The parallel interface consists of 8 bi-directional data lines (D0~D7),RW, and CS. The

RW input High indicates a read operation from the BGDRAM . RW input Low indicates a

write to BGDRAM or Internal Command Registers depending on the status of DCOM

pin input.

The CS input serves as data latch signal (clock).

The BGDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The

Built-in Graphic Display size of the BGDRAM is determined by number of row times the number of column

data RAM (BGDRAM)

(120´33 =3960 bits). Figure as follow is a description of the BGDRAM address map. For

mechanical flexibility, re-mapping on both Segment and Common outputs are provided

Display Timing Generator

This module is an on chip low power RC oscillator circuitry. The oscillator frequency can

be selected in the range of 15kHz to 50kHz by external resistor. One can enable the cir-

cuitry by software command. For external clock provided, feed the clock to OSC2 and

leave OSC1 open.

Rev. 1.00

2

February 24, 2004

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