HI5766KCAZ データシートの表示（PDF） - Intersil
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HI5766KCAZ Datasheet PDF : 16 Pages
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HI5766
Typical Performance Curves (Continued)
3.30
3.20
3.10
3.00
-40
-20
0
20
40
60
80
TEMPERATURE (oC)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
fS = 60 MSPS
fIN = 1MHz
TA = 25oC
100 200 300 400 500 600 700 800 900 1023
FREQUENCY (BIN)
FIGURE 21. DC BIAS VOLTAGE (VDC) vs TEMPERATURE
FIGURE 22. 2048 POINT FFT PLOT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
fS = 60 MSPS
fIN = 10MHz
TA = 25oC
100 200 300 400 500 600 700 800 900 1023
FREQUENCY (BIN)
FIGURE 23. 2048 POINT FFT PLOT
Detailed Description
Theory of Operation
The HI5766 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 24 depicts
the circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal, φ1
and φ2, derived from the master sampling clock. During the
sampling phase, φ1, the input signal is applied to the sampling
capacitors, CS. At the same time the holding capacitors, CH,
are discharged to analog ground. At the falling edge of φ1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase, φ2, the two bottom plates of
the sampling capacitors are connected together and the
holding capacitors are switched to the op amp output nodes.
The charge then redistributes between CS and CH completing
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
differential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch and
CS. The relatively small values of these components result in a
typical full power input bandwidth of 250MHz for the converter.
VIN+
φ1
φ1
CS
φ2
VIN-
φ1
CS
φ1
CH
-+
+-
CH
φ1
VOUT+
VOUT-
φ1
FIGURE 24. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a
11
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