HI-8683 データシートの表示（PDF） - Holt Integrated Circuits
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HI-8683
Holt Integrated Circuits
HI-8683 Datasheet PDF : 11 Pages
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HI-8683, HI-8684
PARITY
ENB
INA
ESD
PROTECTION
INB
HI-8683 ONLY
RINA-10
10KW
RINA
RINB
10KW
RINB-10
25KW
25KW
ESD
PROTECTION
&
LINE
RECEIVER
TESTA
TESTB
HI-8684 ONLY
GAPCLK
RESET
READ
RXA
RXB
CLOCK
&
DATA
DETECT
CLK
PARITY
DETECT
DATA
BIT
COUNT
ERROR
DETECT
ERROR
BIT 32
32-BIT
SHIFT 32
REG.
BIT 32
32-BIT
RECEIVE 32
BUFFER
32-BIT
TO
8-BIT
8
MUX
D0 - D7
GAP
DETECT
BYTE
COUNT
DATA RDY
Figure 1. Block Diagram
FUNCTIONAL DESCRIPTION (cont.)
PROTOCOL DETECTION
GAP DETECTION
ARINC clock and data in the HI-8683 are derived from the
two streams of digital data at the INA and INB inputs and the
resulting One/Zero data is shifted into a 32-bit input register
as illustrated in Figure 3.
In the HI-8684, the One/Zero data shifted into the input reg-
ister is created from either the two digital outputs of the built-
in line receiver (Figure 3) or the TESTA and TESTB inputs
(Figure 4).
For ARINC 561 operation, the INA and INB data streams in-
puts must be derived from the ARINC 561 data, clock and
sync with external logic.
The end of a data word is detected by an internal counter
that times out when a data One or Zero is not received for a
period equal to 16 cycles of the GAPCLK signal. The gap
detection time may vary between 16 and 17 cycles of the
GAPCLK signal since the incoming data and GAPCLK are
not usually synchronous inputs. The required frequency of
GAPCLK is a function of the mininum gap time specified for
the type of ARINC data being received. Table 1 indicates
typical frequencies that may be used for the various data
rates normally encountered.
DATABUS
TYPE
429
BIT PERIOD
(µs)
10
429
69 - 133
575
69 - 133
561
69 - 133
MINIMUM GAP
(µs)
45
310 - 599
310 - 599
103 - 200
GAP CLOCK
MHz
0.75
1.0
1.5
0.1
0.1
0.2
GAP DETECTION
TIME (µs)
21.3 - 22.7
16 - 17
10.7 - 11.3
160 - 170
160 - 170
80 - 85
Table 1 - Typical Gap Detection Times
HOLT INTEGRATED CIRCUITS
3
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