HI-516(1999) データシートの表示（PDF） - Intersil
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HI-516 Datasheet PDF : 8 Pages
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HI-516
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
Analog Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VIN, VOUT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
Digital Input Voltage:
TTL Levels Selected (VDD/LLS Pin = GND or Open)
VA0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V
VA3/SDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
CMOS Levels Selected (VDD/LLS Pin = VDD)
VA0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to (V+) +2V
Thermal Information
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
Maximum Junction Temperature
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Ranges
HI-516-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V;
VDD/LLS = GND. (Note 3) Unless Otherwise Specified
TEST
TEMP
CONDITIONS
(oC)
MIN
-5
TYP
MAX
DYNAMIC CHARACTERISTICS
Access Time, tA
25
-
130
175
Full
-
-
225
Break-Before-Make Delay, tOPEN
Enable Delay (ON), tON(EN)
Enable Delay (OFF), tOFF(EN)
Settling Time
To 0.1%
25
10
20
-
25
-
120
175
25
-
140
175
25
-
250
-
To 0.01%
25
-
800
-
Charge Injection Error
Note 6
25
-
-
20
Off Isolation
Note 7
25
55
-
-
Channel Input Capacitance, CS(OFF)
Channel Output Capacitance,
CD(OFF)
Digital Input Capacitance, CA
Input to Output Capacitance,
CDS(OFF)
DIGITAL INPUT CHARACTERISTICS
25
-
25
-
-
10
-
25
25
-
-
10
25
-
0.02
-
Input Low Threshold, VAL (TTL)
Input High Threshold, VAH (TTL)
Input Low Threshold, VAL (CMOS)
Input High Threshold, VAH (CMOS)
Input Leakage Current, IAH (High)
Note 3
Note 3
Note 3
Note 3
Full
-
-
0.8
Full
2.4
-
-
Full
-
-
0.3VDD
Full
0.7VDD
-
-
Full
-
-
1
UNITS
ns
ns
ns
ns
ns
ns
ns
mV
dB
pF
pF
pF
pF
V
V
V
V
µA
4
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