H8S2602 データシートの表示（PDF） - Renesas Electronics
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H8S2602 Datasheet PDF : 492 Pages
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5.5 Interrupt Exception Handling Vector Table......................................................................... 70
5.6 Interrupt Control Modes and Interrupt Operation ................................................................ 73
5.6.1 Interrupt Control Mode 0 ........................................................................................ 73
5.6.2 Interrupt Control Mode 2 ........................................................................................ 75
5.6.3 Interrupt Exception Handling Sequence ................................................................. 77
5.6.4 Interrupt Response Times ....................................................................................... 79
5.6.5 DTC Activation by Interrupt................................................................................... 80
5.7 Usage Notes ......................................................................................................................... 81
5.7.1 Contention between Interrupt Generation and Disabling........................................ 81
5.7.2 Instructions that Disable Interrupts ......................................................................... 82
5.7.3 When Interrupts are Disabled ................................................................................. 82
5.7.4 Interrupts during Execution of EEPMOV Instruction............................................. 82
Section 6 PC Break Controller (PBC) .................................................................83
6.1 Features................................................................................................................................ 83
6.2 Register Descriptions ........................................................................................................... 85
6.2.1 Break Address Register A (BARA) ........................................................................ 85
6.2.2 Break Address Register B (BARB) ........................................................................ 85
6.2.3 Break Control Register A (BCRA) ......................................................................... 86
6.2.4 Break Control Register B (BCRB).......................................................................... 86
6.3 Operation ............................................................................................................................. 87
6.3.1 PC Break Interrupt Due to Instruction Fetch .......................................................... 87
6.3.2 PC Break Interrupt Due to Data Access.................................................................. 87
6.3.3 Notes on PC Break Interrupt Handling ................................................................... 88
6.3.4 Operation in Transitions to Power-Down Modes ................................................... 88
6.3.5 When Instruction Execution is Delayed by One State ............................................ 89
6.4 Usage Notes ......................................................................................................................... 90
6.4.1 Module Stop Mode Setting ..................................................................................... 90
6.4.2 PC Break Interrupts ................................................................................................ 90
6.4.3 CMFA and CMFB .................................................................................................. 90
6.4.4 PC Break Interrupt when DTC is Bus Master......................................................... 90
6.4.5 PC Break Set for Instruction Fetch at Address Following
BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction............................................... 90
6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction .......................................... 91
6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction............. 91
6.4.8 PC Break Set for Instruction Fetch at
Branch Destination Address of Bcc Instruction...................................................... 91
Rev. 1.00 Jan. 21, 2008 Page xi of xxxii
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