GS9004D データシートの表示（PDF） - Gennum -> Semtech
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GS9004D Datasheet PDF : 4 Pages
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GS9004D CABLE EQUALIZER - DETAILED DEVICE DESCRIPTION
The GS9004D Cable Equalizer is a bipolar integrated circuit This output is integrated by an external AGC filter capacitor
used to equalize SMPTE 259M signals from a co-axial cable. (AGC CAP pin 7), providing a steady control voltage for the
The device is implemented as a fourteen pin SOIC, powered voltage variable filter.
from a single five volt supply. With an operating frequency up
to 400 Mb/s, the equalizer consumes about 285 mW of
power.
A separate signal strength indicator output, (SSI pin 6),
proportional to the amount of AGC, is also provided. As the
filter characteristic is varied automatically by the application
The Serial Digital signal is connected to the input (pins 8, 9) of negative feedback, the amplitude of the equalized signal is
either differentially or single ended with the unused input kept at a constant level which is representative of the original
being decoupled. The equalized signal is generated by amplitude at the transmitter.
passing the cable signal through a voltage variable filter
having a characteristic which closely matches the inverse
cable loss characteristic. Additionally, the variation of the
filter characteristic with control voltage is designed to imitate
The equalized signal is then DC restored, effectively restoring
the logic threshold of the equalized signal to its correct level
irrespective of shifts due to AC coupling.
D the variation of the inverse cable loss characteristic as the
cable length is varied.
As the final stage of signal conditioning, a comparator converts
the analog output of the DC restorer to a regenerated digital
E The amplitude of the equalized signal is monitored by a peak
D detector circuit which produces an output current with a
polarity corresponding to the difference between the desired peak
output signal having pseudo-ECL voltage levels. These
outputs, DATA and DATA, are available from pins 13 and 14
respectively.
N S signal level and the actual peak signal level.
An OUTPUT 'EYE' MONITOR (pin 3) allows verification of
signal integrity after equalization, prior to reslicing.
E N68
+5V
VCC
M IG GND
+
10µ
1.0
1.8p
150
68
SDO4
OM ES 100
EC D 100n
100n
R EW VCC 50
VCC
T 100n
NO R N OEM
VCC
100n
VCC
100n
100n
+
VCC 10
FO SSI
100
1
VCC
2
VCC
3
OEM
4
VCC
5
N/C
6
SSI
7
AGC
DATA 14
DATA 13
12
GND1
11
GND
10
GND
9
IN -
8
IN+
47p
GS9004D
75
SDI
680
680
OEM
113
47p
75
18n
100n
GND
5
SI
6
SI
7
VCC
8
SO2 4
SO2 3
SO1 2
SO1 1
GS9007
VCC
1.0
150
1.8p
68
1.0
1.8p
150
68
1.0
1.8p
150
All resistors in ohms, all capacitors in microfarads,
all inductors in henries unless otherwise stated.
SDO3
SDO2
SDO1
Fig. 1 Test Circuit
ANRITSU
ME522A
OR
TEKTRONIX
TSG422
CABLE
DRIVER
DATA
8281 CABLE
CLOCK
D.U.T.
Fig. 2 Test Set-up 1
3 of 4
CABLE
DRIVER
VERTICAL
IN
OSCILLOSCOPE
TRIGGER
IN
32486 -0
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